From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org, linux-nvdimm@lists.01.org,
linux-pci@vger.kernel.org
Cc: patches@lists.linux.dev, Bjorn Helgaas <helgaas@kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 05/13] cxl/mem: Cache port created by the mem dev
Date: Thu, 6 Jan 2022 16:37:48 -0800 [thread overview]
Message-ID: <20220107003756.806582-6-ben.widawsky@intel.com> (raw)
In-Reply-To: <20220107003756.806582-1-ben.widawsky@intel.com>
Since region programming sees all components in the topology as a port,
it's required that endpoints are treated equally. The easiest way to go
from endpoint to port is to simply cache it at creation time.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
drivers/cxl/cxlmem.h | 2 ++
drivers/cxl/mem.c | 16 ++++++++++------
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 4ea0686e5f84..38d6129499c8 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -36,12 +36,14 @@
* @cxlds: The device state backing this device
* @id: id number of this memdev instance.
* @component_reg_phys: register base of component registers
+ * @port: The port created by this device
*/
struct cxl_memdev {
struct device dev;
struct cdev cdev;
struct cxl_dev_state *cxlds;
int id;
+ struct cxl_port *port;
};
static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 9e6e98e5ea06..2ed7554155d2 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -45,8 +45,8 @@ static int wait_for_media(struct cxl_memdev *cxlmd)
return 0;
}
-static int create_endpoint(struct cxl_memdev *cxlmd,
- struct cxl_port *parent_port)
+static struct cxl_port *create_endpoint(struct cxl_memdev *cxlmd,
+ struct cxl_port *parent_port)
{
struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_port *endpoint;
@@ -54,10 +54,10 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev,
cxlds->component_reg_phys, parent_port);
if (IS_ERR(endpoint))
- return PTR_ERR(endpoint);
+ return endpoint;
dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
- return 0;
+ return endpoint;
}
/**
@@ -123,7 +123,7 @@ static int cxl_mem_probe(struct device *dev)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_dev_state *cxlds = cxlmd->cxlds;
- struct cxl_port *parent_port;
+ struct cxl_port *parent_port, *ep_port;
int rc;
rc = wait_for_media(cxlmd);
@@ -182,7 +182,11 @@ static int cxl_mem_probe(struct device *dev)
goto out;
}
- rc = create_endpoint(cxlmd, parent_port);
+ ep_port = create_endpoint(cxlmd, parent_port);
+ if (IS_ERR(ep_port))
+ rc = PTR_ERR(ep_port);
+ else
+ cxlmd->port = ep_port;
out:
device_unlock(&parent_port->dev);
put_device(&parent_port->dev);
--
2.34.1
next prev parent reply other threads:[~2022-01-07 0:38 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 0:37 [PATCH 00/13] CXL Region driver Ben Widawsky
2022-01-07 0:37 ` [PATCH 01/13] cxl/core: Rename find_cxl_port Ben Widawsky
2022-01-07 0:37 ` [PATCH 02/13] cxl/core: Track port depth Ben Widawsky
2022-01-07 0:37 ` [PATCH 03/13] cxl/region: Add region creation ABI Ben Widawsky
2022-01-07 0:37 ` [PATCH 04/13] cxl/region: Introduce concept of region configuration Ben Widawsky
2022-01-07 0:37 ` Ben Widawsky [this message]
2022-01-07 0:37 ` [PATCH 06/13] cxl/region: Introduce a cxl_region driver Ben Widawsky
2022-01-07 0:37 ` [PATCH 07/13] cxl/acpi: Handle address space allocation Ben Widawsky
2022-01-07 0:37 ` [PATCH 08/13] cxl/region: Address " Ben Widawsky
2022-01-07 0:37 ` [PATCH 09/13] cxl/region: Implement XHB verification Ben Widawsky
2022-01-07 10:07 ` Jonathan Cameron
2022-01-07 11:55 ` Jonathan Cameron
2022-01-11 22:47 ` Ben Widawsky
2022-01-07 10:30 ` Jonathan Cameron
2022-01-07 10:38 ` Jonathan Cameron
2022-01-07 16:32 ` Ben Widawsky
2022-01-11 21:32 ` Ben Widawsky
2022-01-07 0:37 ` [PATCH 10/13] cxl/region: HB port config verification Ben Widawsky
2022-01-07 0:37 ` [PATCH 11/13] cxl/region: Add infrastructure for decoder programming Ben Widawsky
2022-01-07 0:37 ` [PATCH 12/13] cxl/region: Record host bridge target list Ben Widawsky
2022-01-07 18:14 ` Jonathan Cameron
2022-01-07 19:20 ` Dan Williams
2022-01-07 0:37 ` [PATCH 13/13] cxl: Program decoders for regions Ben Widawsky
2022-01-07 16:18 ` Jonathan Cameron
2022-01-07 16:33 ` Ben Widawsky
2022-01-07 17:22 ` Jonathan Cameron
2022-01-11 0:05 ` Ben Widawsky
2022-01-12 14:53 ` Jonathan Cameron
2022-01-12 16:54 ` Ben Widawsky
2022-01-15 18:54 ` [PATCH 00/13] CXL Region driver Ben Widawsky
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