From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: <kishon@ti.com>, <vkoul@kernel.org>, <kw@linux.com>,
<krzysztof.kozlowski@canonical.com>, <p.zabel@pengutronix.de>,
<mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V1 01/10] dt-bindings: Add Tegra234 PCIe clocks and resets
Date: Sat, 5 Feb 2022 21:51:35 +0530 [thread overview]
Message-ID: <20220205162144.30240-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com>
Add the clocks and resets used by the PCIe hardware found on
Tegra234 SoCs.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 25 +++++++++++++++++++-
include/dt-bindings/reset/tegra234-reset.h | 27 +++++++++++++++++++++-
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e1b6ef..106a310a6075 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
@@ -24,8 +24,31 @@
#define TEGRA234_CLK_SDMMC4 123U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA234_CLK_UARTA 155U
+/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
+#define TEGRA234_CLK_PEX1_C6_CORE 161U
+/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
+#define TEGRA234_CLK_PEX2_C7_CORE 171U
+/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
+#define TEGRA234_CLK_PEX2_C8_CORE 172U
+/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
+#define TEGRA234_CLK_PEX2_C9_CORE 173U
+/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
+#define TEGRA234_CLK_PEX2_C10_CORE 187U
/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
+/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
+#define TEGRA234_CLK_PEX0_C0_CORE 220U
+/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
+#define TEGRA234_CLK_PEX0_C1_CORE 221U
+/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
+#define TEGRA234_CLK_PEX0_C2_CORE 222U
+/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
+#define TEGRA234_CLK_PEX0_C3_CORE 223U
+/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
+#define TEGRA234_CLK_PEX0_C4_CORE 224U
+/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
+#define TEGRA234_CLK_PEX1_C5_CORE 225U
+
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA234_CLK_PLLC4 237U
/** @brief 32K input clock provided by PMIC */
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 50e13bced642..2a0c5faf0a7e 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
#define DT_BINDINGS_RESET_TEGRA234_RESET_H
@@ -10,8 +10,33 @@
* @brief Identifiers for Resets controllable by firmware
* @{
*/
+#define TEGRA234_RESET_PEX1_CORE_6 11U
+#define TEGRA234_RESET_PEX1_CORE_6_APB 12U
+#define TEGRA234_RESET_PEX1_COMMON_APB 13U
+#define TEGRA234_RESET_PEX2_CORE_7 14U
+#define TEGRA234_RESET_PEX2_CORE_7_APB 15U
+#define TEGRA234_RESET_PEX2_CORE_8 25U
+#define TEGRA234_RESET_PEX2_CORE_8_APB 26U
+#define TEGRA234_RESET_PEX2_CORE_9 27U
+#define TEGRA234_RESET_PEX2_CORE_9_APB 28U
+#define TEGRA234_RESET_PEX2_CORE_10 56U
+#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
+#define TEGRA234_RESET_PEX2_COMMON_APB 58U
#define TEGRA234_RESET_SDMMC4 85U
#define TEGRA234_RESET_UARTA 100U
+#define TEGRA234_RESET_PEX0_CORE_0 116U
+#define TEGRA234_RESET_PEX0_CORE_1 117U
+#define TEGRA234_RESET_PEX0_CORE_2 118U
+#define TEGRA234_RESET_PEX0_CORE_3 119U
+#define TEGRA234_RESET_PEX0_CORE_4 120U
+#define TEGRA234_RESET_PEX0_CORE_0_APB 121U
+#define TEGRA234_RESET_PEX0_CORE_1_APB 122U
+#define TEGRA234_RESET_PEX0_CORE_2_APB 123U
+#define TEGRA234_RESET_PEX0_CORE_3_APB 124U
+#define TEGRA234_RESET_PEX0_CORE_4_APB 125U
+#define TEGRA234_RESET_PEX0_COMMON_APB 126U
+#define TEGRA234_RESET_PEX1_CORE_5 129U
+#define TEGRA234_RESET_PEX1_CORE_5_APB 130U
/** @} */
--
2.17.1
next prev parent reply other threads:[~2022-02-05 16:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-05 16:21 [PATCH V1 00/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-05 16:21 ` Vidya Sagar [this message]
2022-02-11 14:51 ` [PATCH V1 01/10] dt-bindings: Add Tegra234 PCIe clocks and resets Rob Herring
2022-02-05 16:21 ` [PATCH V1 02/10] dt-bindings: power: Add Tegra234 PCIe power domains Vidya Sagar
2022-02-11 14:52 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 03/10] dt-bindings: memory: Add Tegra234 PCIe memory Vidya Sagar
2022-02-06 11:33 ` Krzysztof Kozlowski
2022-02-24 19:04 ` Thierry Reding
2022-02-11 14:53 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
2022-02-07 6:47 ` Raul Tambre
2022-02-11 14:55 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 05/10] dt-bindings: PCI: tegra: Add device tree support for Tegra234 Vidya Sagar
2022-02-11 14:57 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 07/10] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
2022-02-06 11:29 ` Krzysztof Kozlowski
2022-02-05 16:21 ` [PATCH V1 08/10] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 09/10] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
2022-02-07 17:36 ` Bjorn Helgaas
2022-04-23 7:22 ` Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 10/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-07 18:19 ` Bjorn Helgaas
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