From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: <kishon@ti.com>, <vkoul@kernel.org>, <kw@linux.com>,
<krzysztof.kozlowski@canonical.com>, <p.zabel@pengutronix.de>,
<mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V1 08/10] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234
Date: Sat, 5 Feb 2022 21:51:42 +0530 [thread overview]
Message-ID: <20220205162144.30240-9-vidyas@nvidia.com> (raw)
In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com>
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC
interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
module. For each PCIe lane of a controller, there is a P2U unit
instantiated at hardware level. This driver provides support for the
programming required for each P2U that is going to be used for a PCIe
controller.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
drivers/phy/tegra/phy-tegra194-p2u.c | 48 +++++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 3ee02b9eb04f..1415ca71de38 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -2,7 +2,7 @@
/*
* P2U (PIPE to UPHY) driver for Tegra T194 SoC
*
- * Copyright (C) 2019 NVIDIA Corporation.
+ * Copyright (C) 2019-2022 NVIDIA Corporation.
*
* Author: Vidya Sagar <vidyas@nvidia.com>
*/
@@ -14,6 +14,9 @@
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
+#define P2U_CONTROL_CMN 0x74
+#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)
+
#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
@@ -24,8 +27,17 @@
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
+#define P2U_DIR_SEARCH_CTRL 0xd4
+#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18)
+
+struct tegra_p2u_of_data {
+ bool one_dir_search;
+};
+
struct tegra_p2u {
void __iomem *base;
+ bool skip_sz_protection_en; /* Needed to support two retimers */
+ struct tegra_p2u_of_data *of_data;
};
static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
@@ -44,6 +56,12 @@ static int tegra_p2u_power_on(struct phy *x)
struct tegra_p2u *phy = phy_get_drvdata(x);
u32 val;
+ if (phy->skip_sz_protection_en) {
+ val = p2u_readl(phy, P2U_CONTROL_CMN);
+ val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;
+ p2u_writel(phy, val, P2U_CONTROL_CMN);
+ }
+
val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
@@ -58,6 +76,12 @@ static int tegra_p2u_power_on(struct phy *x)
val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
+ if (phy->of_data->one_dir_search) {
+ val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);
+ val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;
+ p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);
+ }
+
return 0;
}
@@ -77,10 +101,19 @@ static int tegra_p2u_probe(struct platform_device *pdev)
if (!phy)
return -ENOMEM;
+ phy->of_data =
+ (struct tegra_p2u_of_data *)of_device_get_match_data(dev);
+ if (!phy->of_data)
+ return -EINVAL;
+
phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");
if (IS_ERR(phy->base))
return PTR_ERR(phy->base);
+ phy->skip_sz_protection_en =
+ of_property_read_bool(dev->of_node,
+ "nvidia,skip-sz-protect-en");
+
platform_set_drvdata(pdev, phy);
generic_phy = devm_phy_create(dev, NULL, &ops);
@@ -96,9 +129,22 @@ static int tegra_p2u_probe(struct platform_device *pdev)
return 0;
}
+static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
+ .one_dir_search = false,
+};
+
+static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
+ .one_dir_search = true,
+};
+
static const struct of_device_id tegra_p2u_id_table[] = {
{
.compatible = "nvidia,tegra194-p2u",
+ .data = &tegra194_p2u_of_data,
+ },
+ {
+ .compatible = "nvidia,tegra234-p2u",
+ .data = &tegra234_p2u_of_data,
},
{}
};
--
2.17.1
next prev parent reply other threads:[~2022-02-05 16:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-05 16:21 [PATCH V1 00/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 01/10] dt-bindings: Add Tegra234 PCIe clocks and resets Vidya Sagar
2022-02-11 14:51 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 02/10] dt-bindings: power: Add Tegra234 PCIe power domains Vidya Sagar
2022-02-11 14:52 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 03/10] dt-bindings: memory: Add Tegra234 PCIe memory Vidya Sagar
2022-02-06 11:33 ` Krzysztof Kozlowski
2022-02-24 19:04 ` Thierry Reding
2022-02-11 14:53 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
2022-02-07 6:47 ` Raul Tambre
2022-02-11 14:55 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 05/10] dt-bindings: PCI: tegra: Add device tree support for Tegra234 Vidya Sagar
2022-02-11 14:57 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 07/10] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
2022-02-06 11:29 ` Krzysztof Kozlowski
2022-02-05 16:21 ` Vidya Sagar [this message]
2022-02-05 16:21 ` [PATCH V1 09/10] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
2022-02-07 17:36 ` Bjorn Helgaas
2022-04-23 7:22 ` Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 10/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-07 18:19 ` Bjorn Helgaas
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