From: Bjorn Helgaas <helgaas@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, shawnguo@kernel.org,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management support
Date: Wed, 9 Feb 2022 09:36:36 -0600 [thread overview]
Message-ID: <20220209153636.GA557361@bhelgaas> (raw)
In-Reply-To: <1644390156-5940-2-git-send-email-hongxing.zhu@nxp.com>
In subject, s/pcie/PCIe/ or remove it altogether, since I don't think
it adds useful information.
On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote:
> i.MX6QP PCIe supports the RESET logic, thus it can support
> the L2 exit by the reset mechanism.
> Enable the i.MX6QP PCIe suspend/resume operations support.
Add blank line between paragraphs or rewrap into a single paragraph.
Rewrap to fill 75 columns.
What does "L2 exit by reset mechanism" mean? Is this an
i.MX6-specific thing? If not, can you point me to the relevant part
of the PCIe spec?
Bjorn
next prev parent reply other threads:[~2022-02-09 15:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 7:02 [RFC 1/2] ARM: dts: imx6qp-sabresd: Enable pcie support Richard Zhu
2022-02-09 7:02 ` [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management support Richard Zhu
2022-02-09 9:07 ` Lucas Stach
2022-02-10 1:58 ` Hongxing Zhu
2022-02-09 15:36 ` Bjorn Helgaas [this message]
2022-02-10 3:23 ` Hongxing Zhu
2022-02-10 22:04 ` Bjorn Helgaas
2022-02-11 2:05 ` Hongxing Zhu
2022-02-11 16:53 ` Bjorn Helgaas
2022-02-15 3:16 ` Hongxing Zhu
2022-02-09 9:05 ` [RFC 1/2] ARM: dts: imx6qp-sabresd: Enable pcie support Lucas Stach
2022-02-10 1:49 ` Hongxing Zhu
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