Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management support

[Bjorn Helgaas <helgaas@kernel.org>]

[+cc Rafael, beginning of thread:
https://lore.kernel.org/r/1644390156-5940-2-git-send-email-hongxing.zhu@nxp.com]

On Fri, Feb 11, 2022 at 02:05:24AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Bjorn Helgaas <helgaas@kernel.org>
> > Sent: 2022年2月11日 6:05
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: l.stach@pengutronix.de; bhelgaas@google.com;
> > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management
> > support
> > 
> > On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Bjorn Helgaas <helgaas@kernel.org>
> > > > Sent: 2022年2月9日 23:37
> > > > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > > > Cc: l.stach@pengutronix.de; bhelgaas@google.com;
> > > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org;
> > > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > > > <linux-imx@nxp.com>
> > > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power
> > > > management support
> > > >
> > > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote:
> > > > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2
> > > > > exit by the reset mechanism.
> > > > > Enable the i.MX6QP PCIe suspend/resume operations support.
> > 
> > > > What does "L2 exit by reset mechanism" mean?  Is this an
> > > > i.MX6-specific thing?  If not, can you point me to the relevant part
> > > > of the PCIe spec?
> > >
> > > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the
> > > self-reset mechanism.  Thus, it can't reset itself to an initialized
> > > stat when link exit from the L2 or L3 stats.  i.MX6QP PCIe has the
> > > self-reset mechanism, and it can reset itself when link exit from L2
> > > or L3 stats.  The commit description might not accurate.  How about
> > > change them to "i.MX6QP PCIe supports the RESET logic, thus it can
> > > reset itself to the initialized stat when exit from L2 or L3 stats."
> > 
> > Ugh, I have all sorts of questions now, but I don't think I want
> > to know much more about this ;)
> > 
> > Seems like this device requires software assist when bringing the
> > link out of L2 or L3.  Is that allowed per PCIe spec, or is this
> > an erratum?
> > 
> > Does this mean the driver needs to be involved when we take a
> > device out of D3 (where the link was in L2 or L3)?
> 
> Yes, the SW should be involved when bringing the link out of L2 or
> L3.  I looked through the SPEC, didn't find that they are forbidden
> by SPEC.  It might be a design limitation, I think.

OK.  I don't understand all the details of L2 and L3, so I'll take
your word for it that this is allowed by spec.

The case I was wondering about is when software puts a device in
D3hot, which can be done via pci_set_power_state(), without any help
from the imx6 driver.  What state will the link be in, and can we also
put the device back in D0 without help from imx6?

Sec 5.3.2 says L1 is a permissible link state for D3hot, so maybe L2
and L3 are not involved in this case.

Bjorn