* [PATCH v2 1/7] dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 2/7] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings Bhupesh Sharma
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk, Rob Herring
Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to
the one used on SM8250.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index a0ae024c2d0c..a023f97daf84 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -14,6 +14,7 @@
- "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845
+ - "qcom,pcie-sm8150" for sm8150
- "qcom,pcie-sm8250" for sm8250
- "qcom,pcie-ipq6018" for ipq6018
@@ -157,7 +158,7 @@
- "pipe" PIPE clock
- clock-names:
- Usage: required for sc8180x and sm8250
+ Usage: required for sc8180x, sm8150 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary clock
@@ -246,7 +247,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sc8180x, sdm845 and sm8250
+ Usage: required for sc8180x, sdm845, sm8150 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/7] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 1/7] dt-bindings: pci: qcom: Document PCIe bindings " Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 3/7] clk: qcom: gcc: Add PCIE_0_GDSC and PCIE_1_GDSC for SM8150 Bhupesh Sharma
` (4 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk, Rob Herring
Add the following two PCIe PHYs found on SM8150, to the QMP binding:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index e417cd667997..9e0f60e682c4 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -38,6 +38,8 @@ properties:
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm6115-qmp-ufs-phy
+ - qcom,sm8150-qmp-gen3x1-pcie-phy
+ - qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
@@ -333,6 +335,8 @@ allOf:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8150-qmp-gen3x1-pcie-phy
+ - qcom,sm8150-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/7] clk: qcom: gcc: Add PCIE_0_GDSC and PCIE_1_GDSC for SM8150
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 1/7] dt-bindings: pci: qcom: Document PCIe bindings " Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 2/7] dt-bindings: phy: qcom,qmp: Add SM8150 PCIe PHY bindings Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 4/7] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Bhupesh Sharma
` (3 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk
Add the PCIE_0_GDSC and PCIE_1_GDSC defines for SM8150,
so that dts files can use the same.
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index 3e1a91876610..ae9c16410420 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -241,6 +241,8 @@
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
/* GCC GDSCRs */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
#define USB30_PRIM_GDSC 4
#define USB30_SEC_GDSC 5
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/7] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
` (2 preceding siblings ...)
2022-03-01 7:25 ` [PATCH v2 3/7] clk: qcom: gcc: Add PCIE_0_GDSC and PCIE_1_GDSC for SM8150 Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support Bhupesh Sharma
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk, Vinod Koul
SM8150 has multiple (different) PHY versions:
QMP GEN3x1 PHY - 1 lane
QMP GEN3x2 PHY - 2 lanes
Add support for these with relevant init sequence.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 90 +++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 8ea87c69f463..0805c1bab690 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -3294,6 +3294,11 @@ static const char * const sdm845_pciephy_clk_l[] = {
"aux", "cfg_ahb", "ref", "refgen",
};
+/* the pcie phy on sm8150 doesn't have a ref clock */
+static const char * const sm8150_pciephy_clk_l[] = {
+ "aux", "cfg_ahb", "refgen",
+};
+
static const char * const qmp_v4_phy_clk_l[] = {
"aux", "ref_clk_src", "ref", "com_aux",
};
@@ -3583,6 +3588,85 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
.pwrdn_delay_max = 1005, /* us */
};
+static const struct qmp_phy_cfg sm8150_qmp_gen3x1_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
+ .clk_list = sm8150_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .start_ctrl = PCS_START | SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
+static const struct qmp_phy_cfg sm8150_qmp_gen3x2_pciephy_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 2,
+
+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
+ .clk_list = sm8150_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sm8150_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .start_ctrl = PCS_START | SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+
+ .is_dual_lane_phy = true,
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.type = PHY_TYPE_PCIE,
.nlanes = 1,
@@ -6004,6 +6088,12 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm6115-qmp-ufs-phy",
.data = &sm6115_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
+ .data = &sm8150_qmp_gen3x1_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
+ .data = &sm8150_qmp_gen3x2_pciephy_cfg,
}, {
.compatible = "qcom,sm8150-qmp-ufs-phy",
.data = &sm8150_ufsphy_cfg,
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
` (3 preceding siblings ...)
2022-03-01 7:25 ` [PATCH v2 4/7] phy: qcom-qmp: Add SM8150 PCIe QMP PHYs Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 11:43 ` Dmitry Baryshkov
2022-03-01 7:25 ` [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Bhupesh Sharma
2022-03-01 7:25 ` [PATCH v2 7/7] arm64: dts: qcom: sa8155: Enable pcie nodes Bhupesh Sharma
6 siblings, 1 reply; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk, Vinod Koul, Dmitry Baryshkov
The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
SM8250. Hence the support is added reusing the members of ops_2_7_0.
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c19cd506ed3f..66fbc0234888 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
.config_sid = qcom_pcie_config_sid_sm8250,
};
+/* Qcom IP rev.: 1.5.0 */
+static const struct qcom_pcie_ops ops_1_5_0 = {
+ .get_resources = qcom_pcie_get_resources_2_7_0,
+ .init = qcom_pcie_init_2_7_0,
+ .deinit = qcom_pcie_deinit_2_7_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+ .post_init = qcom_pcie_post_init_2_7_0,
+ .post_deinit = qcom_pcie_post_deinit_2_7_0,
+ .config_sid = qcom_pcie_config_sid_sm8250,
+};
+
static const struct qcom_pcie_cfg apq8084_cfg = {
.ops = &ops_1_0_0,
};
@@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
.ops = &ops_2_7_0,
};
+static const struct qcom_pcie_cfg sm8150_cfg = {
+ .ops = &ops_1_5_0,
+};
+
static const struct qcom_pcie_cfg sm8250_cfg = {
.ops = &ops_1_9_0,
};
@@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
+ { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support
2022-03-01 7:25 ` [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support Bhupesh Sharma
@ 2022-03-01 11:43 ` Dmitry Baryshkov
2022-03-02 12:19 ` Bhupesh Sharma
0 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-03-01 11:43 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.linux, lorenzo.pieralisi, agross, bjorn.andersson,
svarbanov, bhelgaas, linux-kernel, robh+dt, sboyd, mturquette,
linux-clk, Vinod Koul
On 01/03/2022 10:25, Bhupesh Sharma wrote:
> The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
> SM8250. Hence the support is added reusing the members of ops_2_7_0.
>
> Cc: Vinod Koul <vkoul@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c19cd506ed3f..66fbc0234888 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
> .config_sid = qcom_pcie_config_sid_sm8250,
> };
>
> +/* Qcom IP rev.: 1.5.0 */
> +static const struct qcom_pcie_ops ops_1_5_0 = {
> + .get_resources = qcom_pcie_get_resources_2_7_0,
> + .init = qcom_pcie_init_2_7_0,
> + .deinit = qcom_pcie_deinit_2_7_0,
> + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> + .post_init = qcom_pcie_post_init_2_7_0,
> + .post_deinit = qcom_pcie_post_deinit_2_7_0,
> + .config_sid = qcom_pcie_config_sid_sm8250,
> +};
> +
This duplicates the ops_1_9_0, doesn't it?
I'd suggest to reuse 1.9.0 structure and add a comment that it's also
used for 1.5.0.
> static const struct qcom_pcie_cfg apq8084_cfg = {
> .ops = &ops_1_0_0,
> };
> @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
> .ops = &ops_2_7_0,
> };
>
> +static const struct qcom_pcie_cfg sm8150_cfg = {
> + .ops = &ops_1_5_0,
> +};
> +
> static const struct qcom_pcie_cfg sm8250_cfg = {
> .ops = &ops_1_9_0,
> };
> @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
> { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
> { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
> + { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
> { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
> { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
> { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support
2022-03-01 11:43 ` Dmitry Baryshkov
@ 2022-03-02 12:19 ` Bhupesh Sharma
0 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-02 12:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, linux-pci, devicetree, bhupesh.linux,
lorenzo.pieralisi, agross, bjorn.andersson, svarbanov, bhelgaas,
linux-kernel, robh+dt, sboyd, mturquette, linux-clk, Vinod Koul
Hi Dmitry,
On Tue, 1 Mar 2022 at 17:13, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 01/03/2022 10:25, Bhupesh Sharma wrote:
> > The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
> > SM8250. Hence the support is added reusing the members of ops_2_7_0.
> >
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index c19cd506ed3f..66fbc0234888 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1487,6 +1487,17 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
> > .config_sid = qcom_pcie_config_sid_sm8250,
> > };
> >
> > +/* Qcom IP rev.: 1.5.0 */
> > +static const struct qcom_pcie_ops ops_1_5_0 = {
> > + .get_resources = qcom_pcie_get_resources_2_7_0,
> > + .init = qcom_pcie_init_2_7_0,
> > + .deinit = qcom_pcie_deinit_2_7_0,
> > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> > + .post_init = qcom_pcie_post_init_2_7_0,
> > + .post_deinit = qcom_pcie_post_deinit_2_7_0,
> > + .config_sid = qcom_pcie_config_sid_sm8250,
> > +};
> > +
>
> This duplicates the ops_1_9_0, doesn't it?
> I'd suggest to reuse 1.9.0 structure and add a comment that it's also
> used for 1.5.0.
Ack. I will fix this in v3.
Regards,
Bhupesh
> > static const struct qcom_pcie_cfg apq8084_cfg = {
> > .ops = &ops_1_0_0,
> > };
> > @@ -1511,6 +1522,10 @@ static const struct qcom_pcie_cfg sdm845_cfg = {
> > .ops = &ops_2_7_0,
> > };
> >
> > +static const struct qcom_pcie_cfg sm8150_cfg = {
> > + .ops = &ops_1_5_0,
> > +};
> > +
> > static const struct qcom_pcie_cfg sm8250_cfg = {
> > .ops = &ops_1_9_0,
> > };
> > @@ -1626,6 +1641,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> > { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
> > { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
> > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
> > + { .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
> > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
> > { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
> > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
` (4 preceding siblings ...)
2022-03-01 7:25 ` [PATCH v2 5/7] PCI: qcom: Add SM8150 SoC support Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
2022-03-01 11:59 ` Dmitry Baryshkov
2022-03-02 0:07 ` Bjorn Helgaas
2022-03-01 7:25 ` [PATCH v2 7/7] arm64: dts: qcom: sa8155: Enable pcie nodes Bhupesh Sharma
6 siblings, 2 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk
Add nodes for the two PCIe controllers founds on the
SM8150 SoC.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++
1 file changed, 243 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 6012322a5984..b97f04ec9c6b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1626,6 +1626,203 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie0: pci@1c00000 {
+ compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu";
+
+ iommus = <&apps_smmu 0x1d80 0x7f>;
+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+ <0x100 &apps_smmu 0x1d81 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ phys = <&pcie0_lane>;
+ phy-names = "pciephy";
+
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x1c0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
+ clock-names = "aux", "cfg_ahb", "refgen";
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie0_lane: phy@1c06200 {
+ reg = <0 0x1c06200 0 0x170>, /* tx */
+ <0 0x1c06400 0 0x200>, /* rx */
+ <0 0x1c06800 0 0x1f0>, /* pcs */
+ <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #phy-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+ };
+ };
+
+ pcie1: pci@1c08000 {
+ compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ iommus = <&apps_smmu 0x1e00 0x7f>;
+ iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
+ <0x100 &apps_smmu 0x1e01 0x1>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ phys = <&pcie1_lane>;
+ phy-names = "pciephy";
+
+ perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c0e000 {
+ compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x1c0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
+ clock-names = "aux", "cfg_ahb", "refgen";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie1_lane: phy@1c0e200 {
+ reg = <0 0x1c0e200 0 0x170>, /* tx0 */
+ <0 0x1c0e400 0 0x200>, /* rx0 */
+ <0 0x1c0ea00 0 0x1f0>, /* pcs */
+ <0 0x1c0e600 0 0x170>, /* tx1 */
+ <0 0x1c0e800 0 0x200>, /* rx1 */
+ <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #phy-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+ };
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default {
drive-strength = <6>;
bias-disable;
};
+
+ pcie0_default_state: pcie0-default {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default {
+ perst {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio103";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
remoteproc_mpss: remoteproc@4080000 {
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
2022-03-01 7:25 ` [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Bhupesh Sharma
@ 2022-03-01 11:59 ` Dmitry Baryshkov
2022-03-02 12:15 ` Bhupesh Sharma
2022-03-02 0:07 ` Bjorn Helgaas
1 sibling, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-03-01 11:59 UTC (permalink / raw)
To: Bhupesh Sharma, linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.linux, lorenzo.pieralisi, agross, bjorn.andersson,
svarbanov, bhelgaas, linux-kernel, robh+dt, sboyd, mturquette,
linux-clk
On 01/03/2022 10:25, Bhupesh Sharma wrote:
> Add nodes for the two PCIe controllers founds on the
> SM8150 SoC.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++
> 1 file changed, 243 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 6012322a5984..b97f04ec9c6b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -1626,6 +1626,203 @@ system-cache-controller@9200000 {
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie0: pci@1c00000 {
> + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
> + reg = <0 0x01c00000 0 0x3000>,
> + <0 0x60000000 0 0xf1d>,
> + <0 0x60000f20 0 0xa8>,
> + <0 0x60001000 0 0x1000>,
> + <0 0x60100000 0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> + <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> + clock-names = "pipe",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "tbu";
> +
> + iommus = <&apps_smmu 0x1d80 0x7f>;
> + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
> + <0x100 &apps_smmu 0x1d81 0x1>;
> +
> + resets = <&gcc GCC_PCIE_0_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_0_GDSC>;
> +
> + phys = <&pcie0_lane>;
> + phy-names = "pciephy";
> +
> + perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
> + enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_default_state>;
> +
> + status = "disabled";
> + };
> +
> + pcie0_phy: phy@1c06000 {
> + compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
> + reg = <0 0x01c06000 0 0x1c0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
> + clock-names = "aux", "cfg_ahb", "refgen";
> +
> + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + status = "disabled";
> +
> + pcie0_lane: phy@1c06200 {
> + reg = <0 0x1c06200 0 0x170>, /* tx */
> + <0 0x1c06400 0 0x200>, /* rx */
> + <0 0x1c06800 0 0x1f0>, /* pcs */
> + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> + clock-names = "pipe0";
> +
> + #phy-cells = <0>;
> + clock-output-names = "pcie_0_pipe_clk";
> + };
> + };
> +
> + pcie1: pci@1c08000 {
> + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
> + reg = <0 0x01c08000 0 0x3000>,
> + <0 0x40000000 0 0xf1d>,
> + <0 0x40000f20 0 0xa8>,
> + <0 0x40001000 0 0x1000>,
> + <0 0x40100000 0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> + interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
This should be 307
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> + clock-names = "pipe",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "tbu";
> +
> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + iommus = <&apps_smmu 0x1e00 0x7f>;
> + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
> + <0x100 &apps_smmu 0x1e01 0x1>;
> +
> + resets = <&gcc GCC_PCIE_1_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_1_GDSC>;
> +
> + phys = <&pcie1_lane>;
> + phy-names = "pciephy";
> +
> + perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
> + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_default_state>;
> +
> + status = "disabled";
> + };
> +
> + pcie1_phy: phy@1c0e000 {
> + compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
> + reg = <0 0x01c0e000 0 0x1c0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
> + clock-names = "aux", "cfg_ahb", "refgen";
> +
> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + status = "disabled";
> +
> + pcie1_lane: phy@1c0e200 {
> + reg = <0 0x1c0e200 0 0x170>, /* tx0 */
> + <0 0x1c0e400 0 0x200>, /* rx0 */
> + <0 0x1c0ea00 0 0x1f0>, /* pcs */
> + <0 0x1c0e600 0 0x170>, /* tx1 */
> + <0 0x1c0e800 0 0x200>, /* rx1 */
> + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> + clock-names = "pipe0";
> +
> + #phy-cells = <0>;
> + clock-output-names = "pcie_1_pipe_clk";
> + };
> + };
> +
> ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> @@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default {
> drive-strength = <6>;
> bias-disable;
> };
> +
> + pcie0_default_state: pcie0-default {
> + perst {
> + pins = "gpio35";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq {
> + pins = "gpio36";
> + function = "pci_e0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake {
> + pins = "gpio37";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + pcie1_default_state: pcie1-default {
> + perst {
> + pins = "gpio102";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq {
> + pins = "gpio103";
> + function = "pci_e1";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake {
> + pins = "gpio104";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> };
>
> remoteproc_mpss: remoteproc@4080000 {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
2022-03-01 11:59 ` Dmitry Baryshkov
@ 2022-03-02 12:15 ` Bhupesh Sharma
0 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-02 12:15 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, linux-pci, devicetree, bhupesh.linux,
lorenzo.pieralisi, agross, bjorn.andersson, svarbanov, bhelgaas,
linux-kernel, robh+dt, sboyd, mturquette, linux-clk
Hi Dmitry,
Thanks for the review.
On Tue, 1 Mar 2022 at 17:29, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On 01/03/2022 10:25, Bhupesh Sharma wrote:
> > Add nodes for the two PCIe controllers founds on the
> > SM8150 SoC.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++
> > 1 file changed, 243 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > index 6012322a5984..b97f04ec9c6b 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -1626,6 +1626,203 @@ system-cache-controller@9200000 {
> > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + pcie0: pci@1c00000 {
> > + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
> > + reg = <0 0x01c00000 0 0x3000>,
> > + <0 0x60000000 0 0xf1d>,
> > + <0 0x60000f20 0 0xa8>,
> > + <0 0x60001000 0 0x1000>,
> > + <0 0x60100000 0 0x100000>;
> > + reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + device_type = "pci";
> > + linux,pci-domain = <0>;
> > + bus-range = <0x00 0xff>;
> > + num-lanes = <1>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > +
> > + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> > + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
> > +
> > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi";
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> > +
> > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> > + <&gcc GCC_PCIE_0_AUX_CLK>,
> > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> > + clock-names = "pipe",
> > + "aux",
> > + "cfg",
> > + "bus_master",
> > + "bus_slave",
> > + "slave_q2a",
> > + "tbu";
> > +
> > + iommus = <&apps_smmu 0x1d80 0x7f>;
> > + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
> > + <0x100 &apps_smmu 0x1d81 0x1>;
> > +
> > + resets = <&gcc GCC_PCIE_0_BCR>;
> > + reset-names = "pci";
> > +
> > + power-domains = <&gcc PCIE_0_GDSC>;
> > +
> > + phys = <&pcie0_lane>;
> > + phy-names = "pciephy";
> > +
> > + perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
> > + enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pcie0_default_state>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + pcie0_phy: phy@1c06000 {
> > + compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
> > + reg = <0 0x01c06000 0 0x1c0>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
> > + clock-names = "aux", "cfg_ahb", "refgen";
> > +
> > + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
> > + reset-names = "phy";
> > +
> > + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
> > + assigned-clock-rates = <100000000>;
> > +
> > + status = "disabled";
> > +
> > + pcie0_lane: phy@1c06200 {
> > + reg = <0 0x1c06200 0 0x170>, /* tx */
> > + <0 0x1c06400 0 0x200>, /* rx */
> > + <0 0x1c06800 0 0x1f0>, /* pcs */
> > + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
> > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> > + clock-names = "pipe0";
> > +
> > + #phy-cells = <0>;
> > + clock-output-names = "pcie_0_pipe_clk";
> > + };
> > + };
> > +
> > + pcie1: pci@1c08000 {
> > + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
> > + reg = <0 0x01c08000 0 0x3000>,
> > + <0 0x40000000 0 0xf1d>,
> > + <0 0x40000f20 0 0xa8>,
> > + <0 0x40001000 0 0x1000>,
> > + <0 0x40100000 0 0x100000>;
> > + reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + device_type = "pci";
> > + linux,pci-domain = <1>;
> > + bus-range = <0x00 0xff>;
> > + num-lanes = <2>;
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > +
> > + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> > +
> > + interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
>
> This should be 307
Oops. Yes, I will fix it in v3.
Thanks,
Bhupesh
> > + interrupt-names = "msi";
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> > +
> > + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> > + <&gcc GCC_PCIE_1_AUX_CLK>,
> > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> > + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> > + clock-names = "pipe",
> > + "aux",
> > + "cfg",
> > + "bus_master",
> > + "bus_slave",
> > + "slave_q2a",
> > + "tbu";
> > +
> > + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> > + assigned-clock-rates = <19200000>;
> > +
> > + iommus = <&apps_smmu 0x1e00 0x7f>;
> > + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
> > + <0x100 &apps_smmu 0x1e01 0x1>;
> > +
> > + resets = <&gcc GCC_PCIE_1_BCR>;
> > + reset-names = "pci";
> > +
> > + power-domains = <&gcc PCIE_1_GDSC>;
> > +
> > + phys = <&pcie1_lane>;
> > + phy-names = "pciephy";
> > +
> > + perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
> > + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pcie1_default_state>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + pcie1_phy: phy@1c0e000 {
> > + compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
> > + reg = <0 0x01c0e000 0 0x1c0>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> > + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
> > + clock-names = "aux", "cfg_ahb", "refgen";
> > +
> > + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> > + reset-names = "phy";
> > +
> > + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
> > + assigned-clock-rates = <100000000>;
> > +
> > + status = "disabled";
> > +
> > + pcie1_lane: phy@1c0e200 {
> > + reg = <0 0x1c0e200 0 0x170>, /* tx0 */
> > + <0 0x1c0e400 0 0x200>, /* rx0 */
> > + <0 0x1c0ea00 0 0x1f0>, /* pcs */
> > + <0 0x1c0e600 0 0x170>, /* tx1 */
> > + <0 0x1c0e800 0 0x200>, /* rx1 */
> > + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
> > + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
> > + clock-names = "pipe0";
> > +
> > + #phy-cells = <0>;
> > + clock-output-names = "pcie_1_pipe_clk";
> > + };
> > + };
> > +
> > ufs_mem_hc: ufshc@1d84000 {
> > compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> > "jedec,ufs-2.0";
> > @@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default {
> > drive-strength = <6>;
> > bias-disable;
> > };
> > +
> > + pcie0_default_state: pcie0-default {
> > + perst {
> > + pins = "gpio35";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + clkreq {
> > + pins = "gpio36";
> > + function = "pci_e0";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + wake {
> > + pins = "gpio37";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + pcie1_default_state: pcie1-default {
> > + perst {
> > + pins = "gpio102";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + clkreq {
> > + pins = "gpio103";
> > + function = "pci_e1";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + wake {
> > + pins = "gpio104";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > };
> >
> > remoteproc_mpss: remoteproc@4080000 {
>
>
> --
> With best wishes
> Dmitry
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
2022-03-01 7:25 ` [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Bhupesh Sharma
2022-03-01 11:59 ` Dmitry Baryshkov
@ 2022-03-02 0:07 ` Bjorn Helgaas
2022-03-02 12:17 ` Bhupesh Sharma
1 sibling, 1 reply; 14+ messages in thread
From: Bjorn Helgaas @ 2022-03-02 0:07 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, linux-pci, devicetree, bhupesh.linux,
lorenzo.pieralisi, agross, bjorn.andersson, svarbanov, bhelgaas,
linux-kernel, robh+dt, sboyd, mturquette, linux-clk
In subject, s/pcie/PCIe/
Since the subject already mentions "sm8150:", maybe the "for SM8150"
is superfluous?
On Tue, Mar 01, 2022 at 12:55:10PM +0530, Bhupesh Sharma wrote:
> Add nodes for the two PCIe controllers founds on the
> SM8150 SoC.
s/founds/found/
Rewrap to fill 75 columns.
> + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
Personally I would use INTA, INTB, etc in the comments to match the
PCI spec usage, but grep says that's a minority view.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
2022-03-02 0:07 ` Bjorn Helgaas
@ 2022-03-02 12:17 ` Bhupesh Sharma
0 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-02 12:17 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-arm-msm, linux-pci, devicetree, bhupesh.linux,
lorenzo.pieralisi, agross, bjorn.andersson, svarbanov, bhelgaas,
linux-kernel, robh+dt, sboyd, mturquette, linux-clk
Hi Bjorn,
On Wed, 2 Mar 2022 at 05:37, Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> In subject, s/pcie/PCIe/
>
> Since the subject already mentions "sm8150:", maybe the "for SM8150"
> is superfluous?
>
> On Tue, Mar 01, 2022 at 12:55:10PM +0530, Bhupesh Sharma wrote:
> > Add nodes for the two PCIe controllers founds on the
> > SM8150 SoC.
>
> s/founds/found/
>
> Rewrap to fill 75 columns.
Sure, I will fix these in v3.
> > + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> > + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>
> Personally I would use INTA, INTB, etc in the comments to match the
> PCI spec usage, but grep says that's a minority view.
Right, I see that most dts (especially the qcom ones) use this
nomenclature (although I have no strong personal opinion about this).
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 7/7] arm64: dts: qcom: sa8155: Enable pcie nodes
2022-03-01 7:25 [PATCH v2 0/7] Add PCIe support for SM8150 SoC Bhupesh Sharma
` (5 preceding siblings ...)
2022-03-01 7:25 ` [PATCH v2 6/7] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150 Bhupesh Sharma
@ 2022-03-01 7:25 ` Bhupesh Sharma
6 siblings, 0 replies; 14+ messages in thread
From: Bhupesh Sharma @ 2022-03-01 7:25 UTC (permalink / raw)
To: linux-arm-msm, linux-pci, devicetree
Cc: bhupesh.sharma, bhupesh.linux, lorenzo.pieralisi, agross,
bjorn.andersson, svarbanov, bhelgaas, linux-kernel, robh+dt,
sboyd, mturquette, linux-clk, Vinod Koul
SA8155p ADP board supports the PCIe0 controller
in the RC mode (only). So add the support for
the same.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 8756c2b25c7e..3f6b3ee404f5 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -387,9 +387,51 @@ &usb_2_qmpphy {
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l18c_0p88>;
+ vdda-pll-supply = <&vreg_l8c_1p2>;
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l18c_0p88>;
+ vdda-pll-supply = <&vreg_l8c_1p2>;
+};
+
&tlmm {
gpio-reserved-ranges = <0 4>;
+ bt_en_default: bt_en_default {
+ mux {
+ pins = "gpio172";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio172";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ wlan_en_default: wlan_en_default {
+ mux {
+ pins = "gpio169";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio169";
+ drive-strength = <16>;
+ output-high;
+ bias-pull-up;
+ };
+ };
+
usb2phy_ac_en1_default: usb2phy_ac_en1_default {
mux {
pins = "gpio113";
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread