From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<michals@xilinx.com>, <robh@kernel.org>,
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port
Date: Wed, 9 Mar 2022 17:30:23 +0530 [thread overview]
Message-ID: <20220309120025.6721-1-bharat.kumar.gogada@xilinx.com> (raw)
Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.
Changes in v3:
- consistency in is_cpm5 flag check expression.
Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
.../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
2 files changed, 72 insertions(+), 8 deletions(-)
--
2.17.1
next reply other threads:[~2022-03-09 12:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 12:00 Bharat Kumar Gogada [this message]
2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port Bharat Kumar Gogada
2022-03-10 13:24 ` Krzysztof Kozlowski
2022-03-14 4:32 ` Bharat Kumar Gogada
2022-03-10 13:33 ` Krzysztof Kozlowski
2022-03-10 19:13 ` Rob Herring
2022-03-14 4:33 ` Bharat Kumar Gogada
2022-03-09 12:00 ` [PATCH v3 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
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