From: Bharat Kumar Gogada <bharatku@xilinx.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Cc: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
Michal Simek <michals@xilinx.com>,
"robh@kernel.org" <robh@kernel.org>
Subject: RE: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
Date: Mon, 14 Mar 2022 04:32:05 +0000 [thread overview]
Message-ID: <BY5PR02MB69476C01D22DA6794C447171A50F9@BY5PR02MB6947.namprd02.prod.outlook.com> (raw)
In-Reply-To: <6f34f80e-da06-337d-167e-2410309e0f4d@canonical.com>
> On 09/03/2022 13:00, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root Port
> > functioning at Gen5 speed.
> >
> > Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> > ---
> > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
> > 1 file changed, 40 insertions(+), 7 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > index 32f4641085bc..97c7229d7f91 100644
> > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> > @@ -14,17 +14,21 @@ allOf:
> >
> > properties:
> > compatible:
> > - const: xlnx,versal-cpm-host-1.00
> > + contains:
> > + enum:
> > + - xlnx,versal-cpm-host-1.00
> > + - xlnx,versal-cpm5-host-1.00
> >
> > reg:
> > - items:
> > - - description: Configuration space region and bridge registers.
> > - - description: CPM system level control and status registers.
> > + description: |
> > + Should contain cpm_slcr, cfg registers location and length.
> > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr.
> > + minItems: 2
> > + maxItems: 3
>
> You removed here list of items, which should stay. See also
> https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bi
> ndings/example-schema.yaml#L91
> how to do it.
>
> >
> > reg-names:
> > - items:
> > - - const: cfg
> > - - const: cpm_slcr
> > + minItems: 2
> > + maxItems: 3
>
> The same.
>
>
Thanks Krzysztof, will fix this in next patch.
next prev parent reply other threads:[~2022-03-14 4:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 12:00 [PATCH v3 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
2022-03-09 12:00 ` [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
2022-03-10 13:24 ` Krzysztof Kozlowski
2022-03-14 4:32 ` Bharat Kumar Gogada [this message]
2022-03-10 13:33 ` Krzysztof Kozlowski
2022-03-10 19:13 ` Rob Herring
2022-03-14 4:33 ` Bharat Kumar Gogada
2022-03-09 12:00 ` [PATCH v3 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
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