* [PATCH v6 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
2022-07-05 10:56 [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
@ 2022-07-05 10:56 ` Bharat Kumar Gogada
2022-07-05 10:56 ` [PATCH v6 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Bharat Kumar Gogada @ 2022-07-05 10:56 UTC (permalink / raw)
To: linux-pci, linux-kernel; +Cc: bhelgaas, michals, Bharat Kumar Gogada
Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.
Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
.../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index cca395317a4c..24ddc2855b94 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -14,17 +14,23 @@ allOf:
properties:
compatible:
- const: xlnx,versal-cpm-host-1.00
+ enum:
+ - xlnx,versal-cpm-host-1.00
+ - xlnx,versal-cpm5-host
reg:
items:
- description: CPM system level control and status registers.
- description: Configuration space region and bridge registers.
+ - description: CPM5 control and status registers.
+ minItems: 2
reg-names:
items:
- const: cpm_slcr
- const: cfg
+ - const: cpm_csr
+ minItems: 2
interrupts:
maxItems: 1
@@ -95,4 +101,34 @@ examples:
interrupt-controller;
};
};
+
+ cpm5_pcie: pcie@fcdd0000 {
+ compatible = "xlnx,versal-cpm5-host";
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <0 72 4>;
+ interrupt-parent = <&gic>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
+ <0 0 0 2 &pcie_intc_1 1>,
+ <0 0 0 3 &pcie_intc_1 2>,
+ <0 0 0 4 &pcie_intc_1 3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+ <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
+ msi-map = <0x0 &its_gic 0x0 0x10000>;
+ reg = <0x00 0xfcdd0000 0x00 0x1000>,
+ <0x06 0x00000000 0x00 0x1000000>,
+ <0x00 0xfce20000 0x00 0x1000000>;
+ reg-names = "cpm_slcr", "cfg", "cpm_csr";
+
+ pcie_intc_1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
};
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v6 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
2022-07-05 10:56 [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
2022-07-05 10:56 ` [PATCH v6 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
@ 2022-07-05 10:56 ` Bharat Kumar Gogada
2022-07-19 18:06 ` [PATCH v6 0/2] Add support for Xilinx " Gogada, Bharat Kumar
2022-07-22 19:24 ` Bjorn Helgaas
3 siblings, 0 replies; 6+ messages in thread
From: Bharat Kumar Gogada @ 2022-07-05 10:56 UTC (permalink / raw)
To: linux-pci, linux-kernel; +Cc: bhelgaas, michals, Bharat Kumar Gogada
Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additional register bit
to enable and handle legacy interrupts.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
drivers/pci/controller/pcie-xilinx-cpm.c | 64 ++++++++++++++++++++++--
1 file changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index c7cd44ed4dfc..65fbcf702a1b 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -35,6 +35,10 @@
#define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)
+#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0
+#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
+#define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
+
/* Interrupt registers definitions */
#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
@@ -98,6 +102,20 @@
/* Phy Status/Control Register definitions */
#define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11)
+enum xilinx_cpm_version {
+ CPM,
+ CPM5,
+};
+
+/**
+ * struct xilinx_cpm_variant - CPM variant information
+ * @version: CPM5 has few changes compared to CPM block.
+ * CPM5 has dedicated register space for control and status registers.
+ */
+struct xilinx_cpm_variant {
+ enum xilinx_cpm_version version;
+};
+
/**
* struct xilinx_cpm_pcie - PCIe port information
* @dev: Device pointer
@@ -109,6 +127,7 @@
* @intx_irq: legacy interrupt number
* @irq: Error interrupt number
* @lock: lock protecting shared register access
+ * @variant: CPM version check pointer
*/
struct xilinx_cpm_pcie {
struct device *dev;
@@ -120,6 +139,7 @@ struct xilinx_cpm_pcie {
int intx_irq;
int irq;
raw_spinlock_t lock;
+ const struct xilinx_cpm_variant *variant;
};
static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +305,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
generic_handle_domain_irq(port->cpm_domain, i);
pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
+ if (port->variant->version) {
+ val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
+ if (val)
+ writel_relaxed(val,
+ port->cpm_base +
+ XILINX_CPM_PCIE_IR_STATUS);
+ }
+
/*
* XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
* CPM SLCR block.
@@ -484,6 +512,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
*/
writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
+
+ if (port->variant->version) {
+ writel(XILINX_CPM_PCIE_IR_LOCAL,
+ port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
+ }
+
/* Enable the Bridge enable bit */
pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -518,7 +552,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
if (IS_ERR(port->cfg))
return PTR_ERR(port->cfg);
- port->reg_base = port->cfg->win;
+ if (port->variant->version) {
+ port->reg_base = devm_platform_ioremap_resource_byname(pdev,
+ "cpm_csr");
+ if (IS_ERR(port->reg_base))
+ return PTR_ERR(port->reg_base);
+ } else {
+ port->reg_base = port->cfg->win;
+ }
return 0;
}
@@ -559,6 +600,8 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
if (!bus)
return -ENODEV;
+ port->variant = of_device_get_match_data(dev);
+
err = xilinx_cpm_pcie_parse_dt(port, bus->res);
if (err) {
dev_err(dev, "Parsing DT failed\n");
@@ -591,9 +634,24 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
return err;
}
+static const struct xilinx_cpm_variant cpm_host = {
+ .version = CPM,
+};
+
+static const struct xilinx_cpm_variant cpm5_host = {
+ .version = CPM5,
+};
+
static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
- { .compatible = "xlnx,versal-cpm-host-1.00", },
- {}
+ {
+ .compatible = "xlnx,versal-cpm-host-1.00",
+ .data = &cpm_host,
+ },
+ {
+ .compatible = "xlnx,versal-cpm5-host",
+ .data = &cpm5_host,
+ },
+ {},
};
static struct platform_driver xilinx_cpm_pcie_driver = {
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port
2022-07-05 10:56 [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada
` (2 preceding siblings ...)
2022-07-19 18:06 ` [PATCH v6 0/2] Add support for Xilinx " Gogada, Bharat Kumar
@ 2022-07-22 19:24 ` Bjorn Helgaas
2022-07-25 4:41 ` Gogada, Bharat Kumar
3 siblings, 1 reply; 6+ messages in thread
From: Bjorn Helgaas @ 2022-07-22 19:24 UTC (permalink / raw)
To: Bharat Kumar Gogada; +Cc: linux-pci, linux-kernel, bhelgaas, michals
On Tue, Jul 05, 2022 at 04:26:44PM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
>
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
> to enable and handle legacy interrupts.
>
> Changes in v6:
> - Added of_device_get_match_data to identify CPM version.
> - Used enum values to differentiate CPM version.
>
> Bharat Kumar Gogada (2):
> dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
> PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
>
> .../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++-
> drivers/pci/controller/pcie-xilinx-cpm.c | 64 ++++++++++++++++++-
> 2 files changed, 98 insertions(+), 4 deletions(-)
Applied to pci/ctrl/xilinx-cpm for v5.20, thanks!
I tweaked the driver patch to test:
if (port->variant->version == CPM5)
instead of just:
if (port->variant->version)
so it doesn't depend on the enum values.
^ permalink raw reply [flat|nested] 6+ messages in thread