From: "Pali Rohár" <pali@kernel.org>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vidya Sagar" <vidyas@nvidia.com>,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro
Date: Tue, 11 Oct 2022 18:16:38 +0200 [thread overview]
Message-ID: <20221011161638.ycxpg3ox2wv63vym@pali> (raw)
In-Reply-To: <220b0fe7-8b7b-cf9b-e28d-d9d81647fb80@nvidia.com>
On Tuesday 11 October 2022 16:42:34 Jon Hunter wrote:
> On 28/09/2022 13:19, Pali Rohár wrote:
> > Simplify pci-tegra.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro
> > for accessing PCI config space.
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> > Please look also at this related patch:
> > https://patchwork.kernel.org/project/linux-pci/patch/20220911113216.14892-1-pali@kernel.org/
> > ---
> > drivers/pci/controller/pci-tegra.c | 11 +++--------
> > 1 file changed, 3 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> > index 5df90d183526..c9924e75e597 100644
> > --- a/drivers/pci/controller/pci-tegra.c
> > +++ b/drivers/pci/controller/pci-tegra.c
> > @@ -417,13 +417,6 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
> > * address (access to which generates correct config transaction) falls in
> > * this 4 KiB region.
> > */
> > -static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
> > - unsigned int where)
> > -{
> > - return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
> > - (PCI_FUNC(devfn) << 8) | (where & 0xff);
> > -}
> > -
> > static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
> > unsigned int devfn,
> > int where)
> > @@ -445,7 +438,9 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
> > unsigned int offset;
> > u32 base;
> > - offset = tegra_pcie_conf_offset(bus->number, devfn, where);
> > + offset = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
> > + PCI_FUNC(devfn), where) &
> > + ~PCI_CONF1_ENABLE;
> > /* move 4 KiB window to offset within the FPCI region */
> > base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
>
>
> Our PCIe test on Tegra124 Jetson TK1 is currently failing on -next and
> bisect points to this commit. Looking at bit closer, the problem appears to
> be the PCI_CONF1_REG_MASK which has a value of 0xfc. Before this patch was
> applied a mask of 0xff was applied to the lower 8-bits of 'where' and now it
> is 0xfc. So this does not work for Tegra as it is.
>
> Let me know if you have any thoughts?
>
> Jon
>
> --
> nvpublic
I see, this is stupid mistake. PCIe config read and write operations
needs to be 4-byte aligned, so normally it is done by calculating 4-byte
aligned base address and then using appropriate cpu load/store
instruction to access just defined size/offset of 4-byte config space
register.
pci-tegra.c is using common helper functions pci_generic_config_read()
and pci_generic_config_write(), which expects final address with offset,
and not 4-byte aligned address.
I'm not sure what should be the proper fix, but for me it looks like
that pci_generic_config_read() and pci_generic_config_write() could be
adjusted to handle it.
In any case, above patch is a regressions and I see there two options
for now:
1) Reverting that patch
2) Adding "offset |= where & 0x3;" after the PCI_CONF1_EXT_ADDRESS()
macro to set also lower 2 bits of accessed register.
Jon, Lorenzo, what do you think? Could you test if 2) is working fine?
next prev parent reply other threads:[~2022-10-11 16:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-28 12:19 [PATCH] PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro Pali Rohár
2022-09-28 14:35 ` Thierry Reding
2022-09-28 14:40 ` Thierry Reding
2022-09-29 8:47 ` Lorenzo Pieralisi
2022-10-11 15:42 ` Jon Hunter
2022-10-11 16:16 ` Pali Rohár [this message]
2022-10-11 16:47 ` Jon Hunter
2022-10-11 16:55 ` Pali Rohár
2022-10-17 7:43 ` Lorenzo Pieralisi
2022-10-17 8:40 ` Jon Hunter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221011161638.ycxpg3ox2wv63vym@pali \
--to=pali@kernel.org \
--cc=bhelgaas@google.com \
--cc=jonathanh@nvidia.com \
--cc=kw@linux.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=robh@kernel.org \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).