From: Matt Ranostay <mranostay@ti.com>
To: <rogerq@kernel.org>, <lpieralisi@kernel.org>, <robh@kernel.org>,
<kw@linux.com>, <bhelgaas@google.com>,
<krzysztof.kozlowski@linaro.org>, <vigneshr@ti.com>,
<tjoseph@cadence.com>, <sergio.paracuellos@gmail.com>,
<pthombar@cadence.com>, <linux-pci@vger.kernel.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Matt Ranostay <mranostay@ti.com>
Subject: [PATCH v7 2/5] PCI: j721e: Add per platform maximum lane settings
Date: Thu, 24 Nov 2022 00:12:18 -0800 [thread overview]
Message-ID: <20221124081221.1206167-3-mranostay@ti.com> (raw)
In-Reply-To: <20221124081221.1206167-1-mranostay@ti.com>
Various platforms have different maximum amount of lanes that can be
selected. Add max_lanes to struct j721e_pcie to allow for detection of this
which is needed to calculate the needed bitmask size for the possible lane
count.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index cc83a8925ce0..8990f58d64d5 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -47,8 +47,6 @@ enum link_status {
#define GENERATION_SEL_MASK GENMASK(1, 0)
-#define MAX_LANES 2
-
struct j721e_pcie {
struct cdns_pcie *cdns_pcie;
struct clk *refclk;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
unsigned int quirk_disable_flr:1;
u32 linkdown_irq_regfield;
unsigned int byte_access_allowed:1;
+ unsigned int max_lanes;
};
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
.quirk_retrain_flag = true,
.byte_access_allowed = false,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j721e_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = LINK_DOWN,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_rc_data = {
@@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
.quirk_detect_quiet_flag = true,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data j7200_pcie_ep_data = {
.mode = PCI_MODE_EP,
.quirk_detect_quiet_flag = true,
.quirk_disable_flr = true,
+ .max_lanes = 2,
};
static const struct j721e_pcie_data am64_pcie_rc_data = {
.mode = PCI_MODE_RC,
.linkdown_irq_regfield = J7200_LINK_DOWN,
.byte_access_allowed = true,
+ .max_lanes = 1,
};
static const struct j721e_pcie_data am64_pcie_ep_data = {
.mode = PCI_MODE_EP,
.linkdown_irq_regfield = J7200_LINK_DOWN,
+ .max_lanes = 1,
};
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -432,7 +437,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
pcie->user_cfg_base = base;
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
- if (ret || num_lanes > MAX_LANES)
+ if (ret || num_lanes > data->max_lanes)
num_lanes = 1;
pcie->num_lanes = num_lanes;
--
2.38.GIT
next prev parent reply other threads:[~2022-11-24 8:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 8:12 [PATCH v7 0/5] PCI: add 4x lane support for pci-j721e controllers Matt Ranostay
2022-11-24 8:12 ` [PATCH v7 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Matt Ranostay
2022-11-26 14:30 ` Krzysztof Kozlowski
2022-11-24 8:12 ` Matt Ranostay [this message]
2022-11-25 12:27 ` [PATCH v7 2/5] PCI: j721e: Add per platform maximum lane settings Roger Quadros
2022-11-24 8:12 ` [PATCH v7 3/5] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-11-25 12:31 ` Roger Quadros
2023-02-02 16:09 ` Lorenzo Pieralisi
2022-11-24 8:12 ` [PATCH v7 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Matt Ranostay
2022-11-26 14:30 ` Krzysztof Kozlowski
2022-11-24 8:12 ` [PATCH v7 5/5] PCI: j721e: add j784s4 PCIe configuration Matt Ranostay
2022-11-25 12:32 ` Roger Quadros
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221124081221.1206167-3-mranostay@ti.com \
--to=mranostay@ti.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=pthombar@cadence.com \
--cc=robh@kernel.org \
--cc=rogerq@kernel.org \
--cc=sergio.paracuellos@gmail.com \
--cc=tjoseph@cadence.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).