From: Roger Quadros <rogerq@kernel.org>
To: Matt Ranostay <mranostay@ti.com>,
lpieralisi@kernel.org, robh@kernel.org, kw@linux.com,
bhelgaas@google.com, krzysztof.kozlowski@linaro.org,
vigneshr@ti.com, tjoseph@cadence.com,
sergio.paracuellos@gmail.com, pthombar@cadence.com,
linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 3/5] PCI: j721e: Add PCIe 4x lane selection support
Date: Fri, 25 Nov 2022 14:31:11 +0200 [thread overview]
Message-ID: <23ecae8e-e4bf-60d9-1fa5-18894834d585@kernel.org> (raw)
In-Reply-To: <20221124081221.1206167-4-mranostay@ti.com>
On 24/11/2022 10:12, Matt Ranostay wrote:
> Add support for setting of two-bit field that allows selection of 4x lane
> PCIe which was previously limited to only 2x lanes.
>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 8990f58d64d5..dab3db9be6d8 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -42,7 +42,6 @@ enum link_status {
> };
>
> #define J721E_MODE_RC BIT(7)
> -#define LANE_COUNT_MASK BIT(8)
> #define LANE_COUNT(n) ((n) << 8)
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
> @@ -52,6 +51,7 @@ struct j721e_pcie {
> struct clk *refclk;
> u32 mode;
> u32 num_lanes;
> + u32 max_lanes;
> void __iomem *user_cfg_base;
> void __iomem *intd_cfg_base;
> u32 linkdown_irq_regfield;
> @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
> {
> struct device *dev = pcie->cdns_pcie->dev;
> u32 lanes = pcie->num_lanes;
> + u32 mask = GENMASK(8, 8);
u32 mask = BIT(8);
> u32 val = 0;
> int ret;
>
> + if (pcie->max_lanes == 4)
> + mask = GENMASK(9, 8);
> +
> val = LANE_COUNT(lanes - 1);
> - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
> + ret = regmap_update_bits(syscon, offset, mask, val);
> if (ret)
> dev_err(dev, "failed to set link count\n");
>
> @@ -439,6 +443,8 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> if (ret || num_lanes > data->max_lanes)
> num_lanes = 1;
> +
> + pcie->max_lanes = data->max_lanes;
> pcie->num_lanes = num_lanes;
>
> if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
Reviewed-by: Roger Quadros <rogerq@kernel.org>
cheers,
-roger
next prev parent reply other threads:[~2022-11-25 12:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 8:12 [PATCH v7 0/5] PCI: add 4x lane support for pci-j721e controllers Matt Ranostay
2022-11-24 8:12 ` [PATCH v7 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Matt Ranostay
2022-11-26 14:30 ` Krzysztof Kozlowski
2022-11-24 8:12 ` [PATCH v7 2/5] PCI: j721e: Add per platform maximum lane settings Matt Ranostay
2022-11-25 12:27 ` Roger Quadros
2022-11-24 8:12 ` [PATCH v7 3/5] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-11-25 12:31 ` Roger Quadros [this message]
2023-02-02 16:09 ` Lorenzo Pieralisi
2022-11-24 8:12 ` [PATCH v7 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Matt Ranostay
2022-11-26 14:30 ` Krzysztof Kozlowski
2022-11-24 8:12 ` [PATCH v7 5/5] PCI: j721e: add j784s4 PCIe configuration Matt Ranostay
2022-11-25 12:32 ` Roger Quadros
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=23ecae8e-e4bf-60d9-1fa5-18894834d585@kernel.org \
--to=rogerq@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-omap@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mranostay@ti.com \
--cc=pthombar@cadence.com \
--cc=robh@kernel.org \
--cc=sergio.paracuellos@gmail.com \
--cc=tjoseph@cadence.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).