From: Abel Vesa <abel.vesa@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-phy@lists.infradead.org
Subject: [PATCH v5 10/12] PCI: qcom: Add SM8550 PCIe support
Date: Tue, 24 Jan 2023 14:47:12 +0200 [thread overview]
Message-ID: <20230124124714.3087948-11-abel.vesa@linaro.org> (raw)
In-Reply-To: <20230124124714.3087948-1-abel.vesa@linaro.org>
Add compatible for both PCIe found on SM8550.
Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
The v4 of this patchset is:
https://lore.kernel.org/all/20230119140453.3942340-11-abel.vesa@linaro.org/
Changes since v4:
* added Mani's R-b tag
Changes since v3:
* renamed cnoc_pcie_sf_axi to cnoc_sf_axi
Changes since v2:
* none
Changes since v1:
* changed the subject line prefix for the patch to match the history,
like Bjorn Helgaas suggested.
* added Konrad's R-b tag
drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 77e5dc7b88ad..0297f86e15c9 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 {
/* 6 clocks typically, 7 for sm8250 */
struct qcom_pcie_resources_2_7_0 {
- struct clk_bulk_data clks[12];
+ struct clk_bulk_data clks[14];
int num_clks;
struct regulator_bulk_data supplies[2];
- struct reset_control *pci_reset;
+ struct reset_control *rst;
};
struct qcom_pcie_resources_2_9_0 {
@@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
unsigned int idx;
int ret;
- res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
- if (IS_ERR(res->pci_reset))
- return PTR_ERR(res->pci_reset);
+ res->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(res->rst))
+ return PTR_ERR(res->rst);
res->supplies[0].supply = "vdda";
res->supplies[1].supply = "vddpe-3v3";
@@ -1205,9 +1205,11 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[idx++].id = "ddrss_sf_tbu";
res->clks[idx++].id = "aggre0";
res->clks[idx++].id = "aggre1";
+ res->clks[idx++].id = "noc_aggr";
res->clks[idx++].id = "noc_aggr_4";
res->clks[idx++].id = "noc_aggr_south_sf";
res->clks[idx++].id = "cnoc_qx";
+ res->clks[idx++].id = "cnoc_sf_axi";
num_opt_clks = idx - num_clks;
res->num_clks = idx;
@@ -1237,17 +1239,17 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
goto err_disable_regulators;
- ret = reset_control_assert(res->pci_reset);
- if (ret < 0) {
- dev_err(dev, "cannot assert pci reset\n");
+ ret = reset_control_assert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset assert failed (%d)\n", ret);
goto err_disable_clocks;
}
usleep_range(1000, 1500);
- ret = reset_control_deassert(res->pci_reset);
- if (ret < 0) {
- dev_err(dev, "cannot deassert pci reset\n");
+ ret = reset_control_deassert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
goto err_disable_clocks;
}
@@ -1828,6 +1830,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
{ }
};
--
2.34.1
next prev parent reply other threads:[~2023-01-24 12:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 12:47 [PATCH v5 00/12] sm8550: Add PCIe HC and PHY support Abel Vesa
2023-01-24 12:47 ` [PATCH v5 01/12] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa
2023-01-26 11:03 ` Krzysztof Kozlowski
2023-01-24 12:47 ` [PATCH v5 02/12] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa
2023-01-24 12:47 ` [PATCH v5 03/12] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 04/12] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 05/12] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 06/12] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa
2023-01-24 12:47 ` [PATCH v5 08/12] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-01-24 12:47 ` [PATCH v5 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-01-26 11:05 ` Krzysztof Kozlowski
2023-01-24 12:47 ` Abel Vesa [this message]
2023-01-24 12:47 ` [PATCH v5 11/12] arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes Abel Vesa
2023-01-24 12:47 ` [PATCH v5 12/12] arm64: dts: qcom: sm8550-mtp: " Abel Vesa
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