From: Marc Zyngier <marc.zyngier@arm.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
"Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Xiaowei Bao <xiaowei.bao@nxp.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leo Li <leoyang.li@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
Mingkai Hu <mingkai.hu@nxp.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI
Date: Wed, 12 Jun 2019 12:22:41 +0100 [thread overview]
Message-ID: <868su7gi9q.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <3b883516-1d63-1504-bdc9-22ac9c6f2d46@arm.com>
On Tue, 11 Jun 2019 18:29:49 +0100,
Marc Zyngier <marc.zyngier@arm.com> wrote:
>
> On 11/06/2019 17:59, Lorenzo Pieralisi wrote:
> > On Fri, Apr 12, 2019 at 08:35:36AM +0000, Z.q. Hou wrote:
> >> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >>
> >> The current code does not support multiple MSIs, so remove
> >> the corresponding flag from the msi_domain_info structure.
> >
> > Please explain me what's the problem before removing multi MSI
> > support.
>
> The reason seems to be the following code in the allocator:
>
> WARN_ON(nr_irqs != 1);
> mutex_lock(&msi->lock);
>
> bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
> if (bit >= msi->num_of_vectors) {
> mutex_unlock(&msi->lock);
> return -ENOSPC;
> }
>
> set_bit(bit, msi->msi_irq_in_use);
>
> So instead of fixing the allocator, the author prefers disabling
> the feature. I'm not sure whether that is an acceptable outcome...
Actually, there is a much deeper issue, and the compose_msi_msg
callback gives a clue:
phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
This thing is using a separate target address per MSI, which is the
killer argument. Bad hardware...
Thanks,
M.
--
Jazz is not dead, it just smells funny.
next prev parent reply other threads:[~2019-06-12 11:22 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-12 8:35 [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 01/20] PCI: mobiveil: Unify register accessors Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 02/20] PCI: mobiveil: Format the code without functionality change Z.q. Hou
2019-07-03 15:10 ` Lorenzo Pieralisi
2019-07-04 2:41 ` Z.q. Hou
2019-07-03 15:19 ` Lorenzo Pieralisi
2019-07-03 15:24 ` Lorenzo Pieralisi
2019-07-04 3:00 ` Z.q. Hou
2019-07-04 10:56 ` Lorenzo Pieralisi
2019-07-05 2:24 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 03/20] PCI: mobiveil: Correct the returned error number Z.q. Hou
2019-07-03 14:17 ` Lorenzo Pieralisi
2019-07-04 2:38 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 04/20] PCI: mobiveil: Remove the flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-06-11 16:59 ` Lorenzo Pieralisi
2019-06-11 17:29 ` Marc Zyngier
2019-06-12 10:54 ` Lorenzo Pieralisi
2019-06-12 11:22 ` Marc Zyngier [this message]
2019-06-12 11:34 ` Z.q. Hou
2019-06-12 13:08 ` Lorenzo Pieralisi
2019-06-15 1:30 ` Z.q. Hou
2019-06-17 9:33 ` Lorenzo Pieralisi
2019-06-17 10:34 ` Z.q. Hou
2019-06-28 11:35 ` Lorenzo Pieralisi
2019-07-01 10:07 ` Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 05/20] PCI: mobiveil: Correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 06/20] PCI: mobiveil: Replace the resource list iteration function Z.q. Hou
2019-04-12 8:35 ` [PATCHv5 07/20] PCI: mobiveil: Use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-06-12 15:13 ` Lorenzo Pieralisi
2019-04-12 8:36 ` [PATCHv5 08/20] PCI: mobiveil: Use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-06-28 16:02 ` Lorenzo Pieralisi
2019-07-01 10:18 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 09/20] PCI: mobiveil: Correct inbound/outbound window setup routines Z.q. Hou
2019-06-28 16:41 ` Lorenzo Pieralisi
2019-07-01 10:24 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 10/20] PCI: mobiveil: Fix the INTx process errors Z.q. Hou
2019-06-12 15:08 ` Lorenzo Pieralisi
2019-06-14 7:08 ` Karthikeyan Mitran
2019-06-14 10:43 ` Lorenzo Pieralisi
2019-06-19 5:28 ` Karthikeyan Mitran
2019-06-19 7:24 ` Z.q. Hou
2019-06-28 17:05 ` Lorenzo Pieralisi
2019-07-01 10:27 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 11/20] PCI: mobiveil: Correct the fixup of Class Code field Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 12/20] PCI: mobiveil: Move the link up waiting out of mobiveil_host_init() Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 13/20] PCI: mobiveil: Move IRQ chained handler setup out of DT parse Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 14/20] PCI: mobiveil: Initialize Primary/Secondary/Subordinate bus numbers Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 15/20] PCI: mobiveil: Fix the checking of valid device Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 16/20] PCI: mobiveil: Add link up condition check Z.q. Hou
2019-06-11 17:17 ` Lorenzo Pieralisi
2019-06-12 11:36 ` Z.q. Hou
2019-04-12 8:36 ` [PATCHv5 17/20] PCI: mobiveil: Complete initialization of host even if no PCIe link Z.q. Hou
2019-06-12 14:34 ` Lorenzo Pieralisi
2019-06-15 2:34 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 18/20] PCI: mobiveil: Disable IB and OB windows set by bootloader Z.q. Hou
2019-06-12 16:23 ` Lorenzo Pieralisi
2019-06-15 5:03 ` Z.q. Hou
2019-06-17 9:30 ` Lorenzo Pieralisi
2019-06-17 10:42 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Z.q. Hou
2019-06-12 13:54 ` Lorenzo Pieralisi
2019-06-15 1:13 ` Z.q. Hou
2019-06-17 9:29 ` Lorenzo Pieralisi
2019-06-17 10:16 ` Z.q. Hou
2019-04-12 8:37 ` [PATCHv5 20/20] dt-bindings: PCI: mobiveil: Change gpio_slave and apb_csr to optional Z.q. Hou
2019-07-03 10:33 ` [PATCHv5 00/20] PCI: mobiveil: fixes for Mobiveil PCIe Host Bridge IP driver Lorenzo Pieralisi
2019-07-04 2:36 ` Z.q. Hou
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