linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Thomas Gleixner <tglx@linutronix.de>
To: Sean V Kelley <sean.v.kelley@linux.intel.com>,
	bhelgaas@google.com, corbet@lwn.net, mingo@redhat.com,
	bp@alien8.de
Cc: x86@kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	kar.hin.ong@ni.com, sassmann@kpanic.de,
	Sean V Kelley <sean.v.kelley@linux.intel.com>
Subject: Re: [PATCH 0/2] Add boot interrupt quirk mechanism for Xeon chipsets
Date: Sat, 15 Feb 2020 10:24:57 +0100	[thread overview]
Message-ID: <8736bctd7a.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200214213313.66622-1-sean.v.kelley@linux.intel.com>

Sean V Kelley <sean.v.kelley@linux.intel.com> writes:
> When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
> Real-Time threaded interrupts), many chipsets redirect IRQs on
> this line to the legacy PCH and in turn the base IO-APIC in the
> system. The unhandled interrupts on the base IO-APIC will be
> identified by the Linux kernel as Spurious Interrupts and can
> lead to disabled IRQ lines.
>
> Disabling this legacy PCI interrupt routing is chipset-specific and
> varies in mechanism between chipset vendors and across generations.
> In some cases the mechanism is exposed to BIOS but not all BIOS
> vendors choose to pick it up. With the increasing usage of RT as it
> marches towards mainline, additional issues have been raised with
> more recent Xeon chipsets.
>
> This patchset disables the boot interrupt on these Xeon chipsets where
> this is possible with an additional mechanism.  In addition, this
> patchset includes documentation covering the background of this quirk.

Well done! The documentation is really appreciated!

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>

  parent reply	other threads:[~2020-02-15  9:25 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 21:33 [PATCH 0/2] Add boot interrupt quirk mechanism for Xeon chipsets Sean V Kelley
2020-02-14 21:33 ` [PATCH 1/2] pci: " Sean V Kelley
2020-02-14 21:33 ` [PATCH 2/2] Documentation:PCI: Add background on Boot Interrupts Sean V Kelley
2020-02-15  9:24 ` Thomas Gleixner [this message]
2020-02-15  9:26   ` [PATCH 0/2] Add boot interrupt quirk mechanism for Xeon chipsets Thomas Gleixner

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=8736bctd7a.fsf@nanos.tec.linutronix.de \
    --to=tglx@linutronix.de \
    --cc=bhelgaas@google.com \
    --cc=bp@alien8.de \
    --cc=corbet@lwn.net \
    --cc=kar.hin.ong@ni.com \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=sassmann@kpanic.de \
    --cc=sean.v.kelley@linux.intel.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).