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From: Thomas Gleixner <tglx@linutronix.de>
To: "Stefan Bühler" <stefan.buehler@tik.uni-stuttgart.de>,
	sean.v.kelley@linux.intel.com
Cc: bhelgaas@google.com, bp@alien8.de, corbet@lwn.net,
	kar.hin.ong@ni.com, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	mingo@redhat.com, sassmann@kpanic.de, x86@kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)
Date: Mon, 30 Nov 2020 11:48:36 +0100	[thread overview]
Message-ID: <87r1obi0hn.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <7b54abab-fe38-4035-7c23-1f7456359c9e@tik.uni-stuttgart.de>

Stefan,

On Fri, Nov 27 2020 at 10:17, Stefan Bühler wrote:
> On 11/27/20 12:45 AM, Thomas Gleixner wrote:
>> Can you please run this as root so the Capabilities are accessible?
>
> My bad, sorry. I did intend to run it as root, but should have checked
> the output.  Again see attached file.

No problem.

> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode])
> 	Physical Slot: 1
> 	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
> 	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> 	Latency: 0, Cache Line Size: 32 bytes
> 	Interrupt: pin A routed to IRQ 16
> 	NUMA node: 0
> 	Bus: primary=05, secondary=06, subordinate=06, sec-latency=64
> 	I/O behind bridge: 0000e000-0000efff
> 	Memory behind bridge: fb400000-fb4fffff
> 	Prefetchable memory behind bridge: fff00000-000fffff
> 	Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
> 	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
> 		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> 	Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
> 		Address: 0000000000000000  Data: 0000

So the bridge would support MSI, but obviously the devices on the PCI
side do not.

> 06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950])
> 	Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
> 	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
> 	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> 	Interrupt: pin A routed to IRQ 16
> 	NUMA node: 0
> 	Region 0: I/O ports at e0e0 [size=32]
> 	Region 1: Memory at fb407000 (32-bit, non-prefetchable) [size=4K]
> 	Region 2: I/O ports at e0c0 [size=32]
> 	Region 3: Memory at fb406000 (32-bit, non-prefetchable) [size=4K]
> 	Capabilities: [40] Power Management version 1
> 		Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-)
> 		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

But that should still work because the boot interrupt quirk should not
affect interrupts which are routed through the IOAPIC.

Sean, any idea what's going on here?

Thanks,

        tglx

      reply	other threads:[~2020-11-30 10:51 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20 19:29 [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets Sean V Kelley
2020-02-20 19:29 ` [PATCH v2 1/2] " Sean V Kelley
2020-02-20 19:29 ` [PATCH v2 2/2] Documentation:PCI: Add background on Boot Interrupts Sean V Kelley
2020-02-27 22:49 ` [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets Bjorn Helgaas
     [not found] ` <b2da25c8-121a-b241-c028-68e49bab0081@tik.uni-stuttgart.de>
2020-11-25 11:54   ` boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets) Thomas Gleixner
2020-11-25 13:41     ` Stefan Bühler
2020-11-26 23:45       ` Thomas Gleixner
2020-11-27  9:17         ` Stefan Bühler
2020-11-30 10:48           ` Thomas Gleixner [this message]

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