From: Stanimir Varbanov <svarbanov@mm-sol.com>
To: Ansuel Smith <ansuelsmth@gmail.com>, Andy Gross <agross@kernel.org>
Cc: Sham Muthayyan <smuthayy@codeaurora.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support
Date: Fri, 3 Apr 2020 12:01:01 +0300 [thread overview]
Message-ID: <8e0ada17-c858-59d2-8d5c-5129e7625f33@mm-sol.com> (raw)
In-Reply-To: <20200402121148.1767-11-ansuelsmth@gmail.com>
Hi Ansuel,
On 4/2/20 3:11 PM, Ansuel Smith wrote:
> From: Sham Muthayyan <smuthayy@codeaurora.org>
>
> Add Force GEN1 support needed in some ipq806x board
> that needs to limit some pcie line to gen1 for some
> hardware limitation.
> This is set by the max-link-speed dts entry and needed
> by some soc based on ipq806x. (for example Netgear R7800
> router)
>
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8047ac7dc8c7..2212e9498b91 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -27,6 +27,7 @@
> #include <linux/slab.h>
> #include <linux/types.h>
>
> +#include "../../pci.h"
This looks suspiciously (even ugly), but I saw that the other users of
of_pci_get_max_link_speed is doing the same.
Bjorn H. : do you know why the prototype is there? Perhaps it must be in
linux/of_pci.h.
> #include "pcie-designware.h"
>
> #define PCIE20_PARF_SYS_CTRL 0x00
> @@ -99,6 +100,8 @@
> #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define SLV_ADDR_SPACE_SZ 0x10000000
>
> +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
tabs instead of spaces and hex numbers should be lower-case
> +
> #define DEVICE_TYPE_RC 0x4
>
> #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
> @@ -199,6 +202,7 @@ struct qcom_pcie {
> struct phy *phy;
> struct gpio_desc *reset;
> const struct qcom_pcie_ops *ops;
> + bool force_gen1;
could you rename this and make it int:
int gen;
> };
>
> #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
> @@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>
> /* wait for clock acquisition */
> usleep_range(1000, 1500);
add a blank line here
> + if (pcie->force_gen1) {
if (pcie->gen == 1) {
> + writel_relaxed((readl_relaxed(
> + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
> + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
> + }
why you are using writel/readl_relaxed ?
Also could you split the line to two:
val = read()
write(val | 1, address)
>
>
> /* Set the Max TLP size to 2K, instead of using default of 4K */
> @@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
> goto err_pm_runtime_put;
> }
>
> + ret = of_pci_get_max_link_speed(pdev->dev.of_node);> + if (ret == 1)
> + pcie->force_gen1 = true;
drop this, handle ret < 0 and default to generation 2
pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
if (pcie->gen < 0)
pcie->gen = 2;
> +
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
> pcie->parf = devm_ioremap_resource(dev, res);
> if (IS_ERR(pcie->parf)) {
>
--
regards,
Stan
next prev parent reply other threads:[~2020-04-03 9:01 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 12:11 [PATCH v2 00/10] Multiple fixes in PCIe qcom driver Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver Ansuel Smith
2020-04-08 8:50 ` Stanimir Varbanov
2020-04-08 12:36 ` R: " ansuelsmth
2020-04-08 12:48 ` Stanimir Varbanov
2020-04-08 12:55 ` R: " ansuelsmth
2020-04-08 13:06 ` Stanimir Varbanov
2020-04-02 12:11 ` [PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom,pcie Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 03/10] PCIe: qcom: change duplicate PCI reset to phy reset Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 05/10] PCIe: qcom: add missing reset for ipq806x Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom,pcie Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming Ansuel Smith
2020-04-08 8:50 ` Stanimir Varbanov
2020-04-08 12:38 ` R: " ansuelsmth
2020-04-08 13:18 ` Stanimir Varbanov
2020-04-02 12:11 ` [PATCH v2 08/10] PCIe: qcom: add ipq8064 rev2 variant and set tx term offset Ansuel Smith
2020-04-02 12:11 ` [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie Ansuel Smith
2020-04-14 17:07 ` Rob Herring
2020-04-02 12:11 ` [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support Ansuel Smith
2020-04-03 9:01 ` Stanimir Varbanov [this message]
2020-04-14 17:09 ` Rob Herring
2020-04-03 9:01 ` [PATCH v2 00/10] Multiple fixes in PCIe qcom driver Stanimir Varbanov
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