From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Bingbu Cao <bingbu.cao@intel.com>
Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org,
linux-pci@vger.kernel.org, iommu@lists.linux-foundation.org,
dwmw2@infradead.org, baolu.lu@linux.intel.com, joro@8bytes.org,
will@kernel.org, bhelgaas@google.com, rajatja@google.com,
grundler@chromium.org, tfiga@chromium.org,
senozhatsky@chromium.org, sakari.ailus@linux.intel.com,
bingbu.cao@linux.intel.com
Subject: Re: [RESEND v2] iommu/vt-d: Use passthrough mode for the Intel IPUs
Date: Tue, 20 Apr 2021 13:21:57 +0300 [thread overview]
Message-ID: <YH6rRUXyNdC6DDzQ@smile.fi.intel.com> (raw)
In-Reply-To: <1618886913-6594-1-git-send-email-bingbu.cao@intel.com>
On Tue, Apr 20, 2021 at 10:48:33AM +0800, Bingbu Cao wrote:
> Intel IPU(Image Processing Unit) has its own (IO)MMU hardware,
> The IPU driver allocates its own page table that is not mapped
> via the DMA, and thus the Intel IOMMU driver blocks access giving
> this error:
>
> DMAR: DRHD: handling fault status reg 3
> DMAR: [DMA Read] Request device [00:05.0] PASID ffffffff
> fault addr 76406000 [fault reason 06] PTE Read access is not set
>
> As IPU is not an external facing device which is not risky, so use
> IOMMU passthrough mode for Intel IPUs.
I'm wondering if IPU MMU should be described properly in the DMAR table.
--
With Best Regards,
Andy Shevchenko
prev parent reply other threads:[~2021-04-20 10:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-20 2:48 [RESEND v2] iommu/vt-d: Use passthrough mode for the Intel IPUs Bingbu Cao
2021-04-20 9:13 ` Sakari Ailus
2021-04-20 17:30 ` Grant Grundler
2021-04-20 10:20 ` Andy Shevchenko
2021-04-20 10:34 ` Bingbu Cao
2021-04-20 10:56 ` Sakari Ailus
2021-04-20 11:55 ` Andy Shevchenko
2021-04-20 14:37 ` Sakari Ailus
2021-04-20 14:54 ` Andy Shevchenko
2021-04-20 15:27 ` Sakari Ailus
2021-04-20 10:21 ` Andy Shevchenko [this message]
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