From: "Derrick, Jonathan" <jonathan.derrick@intel.com>
To: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
Cc: "kbusch@kernel.org" <kbusch@kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"helgaas@kernel.org" <helgaas@kernel.org>
Subject: Re: [PATCH 3/3] PCI: vmd: Use managed irq affinities
Date: Mon, 18 Nov 2019 16:43:47 +0000 [thread overview]
Message-ID: <f44859e7a0a398a50439453f682433ed26c18bd3.camel@intel.com> (raw)
In-Reply-To: <20191118104905.GB32355@e121166-lin.cambridge.arm.com>
On Mon, 2019-11-18 at 10:49 +0000, Lorenzo Pieralisi wrote:
> On Wed, Nov 06, 2019 at 08:33:01PM +0000, Derrick, Jonathan wrote:
> > On Thu, 2019-11-07 at 05:27 +0900, Keith Busch wrote:
> > > On Wed, Nov 06, 2019 at 08:14:41PM +0000, Derrick, Jonathan wrote:
> > > > Yes that problem exists today
> > >
> > > Not really, because we're currently using unamanged interrupts which
> > > migrate to online CPUs. It's only the managed ones that don't migrate
> > > because they have a unchangeable affinity.
> > >
> > > > and this set limits the exposure as it's
> > > > a rare case where you have a child NVMe device with fewer than 32
> > > > vectors.
> > >
> > > I'm deeply skeptical that is the case. Even the P3700 has only 31 IO
> > > queues, yielding 31 vectors for IO services, so that already won't work
> > > with this scheme.
> > >
> > Darn you're right. At one point I had VMD vector 1 using NVMe AQ,
> > leaving the 31 remaining VMD vectors for NVMe IO queues. This would
> > have lined up perfectly. Had changed it last minute and that does break
> > the scheme for P3700....
> >
> > > But assuming you wanted to only use devices that have at least 32 IRQ
> > > vectors, the nvme driver also allows users to carve those vectors up
> > > into fully affinitized sets for different services (read vs. write is
> > > the one the block stack supports), which would also break if alignment
> > > to the parent device's IRQ setup is required.
> >
> > Wasn't aware of this. Fair enough.
>
> Marked the series with "Changes Requested", waiting for a new
> version.
>
> Lorenzo
This will need an entirely different strategy to be useful, so can be
dropped for now.
Thank you,
Jon
next prev parent reply other threads:[~2019-11-18 16:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-06 11:40 [PATCH 0/3] PCI: vmd: Reducing tail latency by affining to the storage stack Jon Derrick
2019-11-06 11:40 ` [PATCH 1/3] PCI: vmd: Reduce VMD vectors using NVMe calculation Jon Derrick
2019-11-06 18:02 ` Keith Busch
2019-11-06 19:51 ` Derrick, Jonathan
2019-11-06 11:40 ` [PATCH 2/3] PCI: vmd: Align IRQ lists with child device vectors Jon Derrick
2019-11-06 18:06 ` Keith Busch
2019-11-06 20:14 ` Derrick, Jonathan
2019-11-06 11:40 ` [PATCH 3/3] PCI: vmd: Use managed irq affinities Jon Derrick
2019-11-06 18:10 ` Keith Busch
2019-11-06 20:14 ` Derrick, Jonathan
2019-11-06 20:27 ` Keith Busch
2019-11-06 20:33 ` Derrick, Jonathan
2019-11-18 10:49 ` Lorenzo Pieralisi
2019-11-18 16:43 ` Derrick, Jonathan [this message]
2019-11-07 9:39 ` [PATCH 0/3] PCI: vmd: Reducing tail latency by affining to the storage stack Christoph Hellwig
2019-11-07 14:12 ` Derrick, Jonathan
2019-11-07 15:37 ` hch
2019-11-07 15:40 ` Derrick, Jonathan
2019-11-07 15:42 ` hch
2019-11-07 15:47 ` Derrick, Jonathan
2019-11-11 17:03 ` hch
2022-12-23 2:33 ` Kai-Heng Feng
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