From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Niklas Cassel <niklas.cassel@axis.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Niklas Cassel <niklass@axis.com>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq
Date: Wed, 20 Dec 2017 19:32:54 +0000 [thread overview]
Message-ID: <fd89cef7-ffab-7d1b-162f-8a155c4576be@synopsys.com> (raw)
In-Reply-To: <20171219232940.659-7-niklas.cassel@axis.com>
Hi,
Às 11:29 PM de 12/19/2017, Niklas Cassel escreveu:
> Add a generic function for raising MSI irqs that can be used by all
> DWC based controllers.
>
> Note that certain controllers, like DRA7xx, have a special convenience
> register for raising MSI irqs that doesn't require you to explicitly map
> the MSI address. Therefore, it is likely that certain drivers will
> not use this generic function, even if they can.
>
> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> ---
> drivers/pci/dwc/pcie-designware-ep.c | 35 +++++++++++++++++++++++++++++++++++
> drivers/pci/dwc/pcie-designware.h | 9 +++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
> index 700ed2f4becf..c5aa1cac5041 100644
> --- a/drivers/pci/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -282,6 +282,41 @@ static const struct pci_epc_ops epc_ops = {
> .stop = dw_pcie_ep_stop,
> };
>
> +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
> + u8 interrupt_num)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct pci_epc *epc = ep->epc;
> + u16 msg_ctrl, msg_data;
> + u32 msg_addr_lower, msg_addr_upper;
> + u64 msg_addr;
> + bool has_upper;
> + int ret;
> +
> + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
> + msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
> + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
> + msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
> + if (has_upper) {
> + msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
> + msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
> + } else {
> + msg_addr_upper = 0;
> + msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
> + }
> + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
> + ret = dw_pcie_ep_map_addr(epc, ep->msi_mem_phys, msg_addr,
> + epc->mem->page_size);
> + if (ret)
> + return ret;
> +
> + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
> +
> + dw_pcie_ep_unmap_addr(epc, ep->msi_mem_phys);
> +
> + return 0;
> +}
> +
> void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> {
> struct pci_epc *epc = ep->epc;
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index 37dfad8d003f..24edac035160 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -106,6 +106,8 @@
> #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
> #define MSI_MESSAGE_ADDR_L32 0x54
> #define MSI_MESSAGE_ADDR_U32 0x58
> +#define MSI_MESSAGE_DATA_32 0x58
> +#define MSI_MESSAGE_DATA_64 0x5C
>
> /*
> * Maximum number of MSI IRQs can be 256 per controller. But keep
> @@ -338,6 +340,7 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
> void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
> int dw_pcie_ep_init(struct dw_pcie_ep *ep);
> void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
> +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 interrupt_num);
> void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
> #else
> static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> @@ -353,6 +356,12 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> {
> }
>
> +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
> + u8 interrupt_num)
> +{
> + return 0;
> +}
> +
> static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> {
> }
>
Acked-by: Joao Pinto <jpinto@synopsys.com>
next prev parent reply other threads:[~2017-12-20 19:32 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-19 23:29 [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 01/18] PCI: dwc: Use the DMA-API to get the MSI address Niklas Cassel
2017-12-20 19:10 ` Joao Pinto
2017-12-21 16:43 ` Jingoo Han
2020-09-23 23:18 ` Rob Herring
2017-12-19 23:29 ` [PATCH v6 02/18] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-12-20 19:17 ` Joao Pinto
2017-12-21 16:44 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 03/18] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-12-20 19:18 ` Joao Pinto
2017-12-21 16:45 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 04/18] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-12-20 19:30 ` Joao Pinto
2017-12-21 16:46 ` Jingoo Han
2017-12-19 23:29 ` [PATCH v6 05/18] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 06/18] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-12-20 19:32 ` Joao Pinto [this message]
2017-12-21 16:47 ` Jingoo Han
2017-12-26 12:50 ` Kishon Vijay Abraham I
2017-12-27 22:29 ` Niklas Cassel
2017-12-28 8:06 ` Kishon Vijay Abraham I
2017-12-28 14:39 ` Kishon Vijay Abraham I
2017-12-28 22:43 ` Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 07/18] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 08/18] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 09/18] PCI: dwc: dra7xx: Help compiler to remove unused code Niklas Cassel
2017-12-20 5:58 ` Kishon Vijay Abraham I
2017-12-19 23:29 ` [PATCH v6 10/18] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 11/18] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 12/18] PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 13/18] bindings: PCI: artpec: Add support for endpoint mode Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 14/18] PCI: dwc: artpec6: " Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 15/18] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-12-20 5:52 ` Kishon Vijay Abraham I
2017-12-19 23:29 ` [PATCH v6 16/18] PCI: dwc: artpec6: Deassert the core before waiting for PHY Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 17/18] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC Niklas Cassel
2017-12-19 23:29 ` [PATCH v6 18/18] PCI: dwc: artpec6: " Niklas Cassel
2017-12-20 17:34 ` [PATCH v6 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Lorenzo Pieralisi
2017-12-20 19:47 ` Joao Pinto
2017-12-20 23:22 ` Niklas Cassel
2017-12-21 9:23 ` Joao Pinto
2017-12-21 10:02 ` Lorenzo Pieralisi
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