* [PATCH] Delete some unusefull operations for centaur CPU/platform
@ 2018-03-02 4:11 David Wang
2018-03-02 11:31 ` Rafael J. Wysocki
2018-03-04 9:31 ` Ingo Molnar
0 siblings, 2 replies; 7+ messages in thread
From: David Wang @ 2018-03-02 4:11 UTC (permalink / raw)
To: rjw, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm, linux-kernel
Cc: brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo,
cobechen, jiangbowang, David Wang
For Centaur CPU, the ucode will make sure that each CPU core can keep cache
coherency with each other when the CPU core entering to any C state. So the
cache flush operations when enter C3 is not necessary and will cause large
C3 enter/exit latency.
And the bus master disable operation when CPU core entering C3 state is not
needed too. Because the chipset will automatically do this operation.
Signed-off-by: David Wang <davidwang@zhaoxin.com>
---
arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index dde437f..1cd357b 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
if (c->x86_vendor == X86_VENDOR_INTEL &&
(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
flags->bm_control = 0;
+
+ if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+ /*
+ * on all centaur CPUs, sw need not execute cache flush operation
+ * when entering C3 type State.
+ *
+ * On all Centaur platforms, sw need not execute ARB_DISABLE while
+ * entering C3 type state.
+ */
+ flags->bm_check = 1;
+ flags->bm_control = 0;
+ }
}
EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] Delete some unusefull operations for centaur CPU/platform
2018-03-02 4:11 [PATCH] Delete some unusefull operations for centaur CPU/platform David Wang
@ 2018-03-02 11:31 ` Rafael J. Wysocki
2018-03-04 9:31 ` Ingo Molnar
1 sibling, 0 replies; 7+ messages in thread
From: Rafael J. Wysocki @ 2018-03-02 11:31 UTC (permalink / raw)
To: David Wang
Cc: len.brown, pavel, tglx, mingo, hpa, x86, linux-pm, linux-kernel,
brucechang, cooperyan, qiyuanwang, benjaminpan, lukelin, timguo,
cobechen, jiangbowang
On Friday, March 2, 2018 5:11:48 AM CET David Wang wrote:
> For Centaur CPU, the ucode will make sure that each CPU core can keep cache
> coherency with each other when the CPU core entering to any C state. So the
> cache flush operations when enter C3 is not necessary and will cause large
> C3 enter/exit latency.
> And the bus master disable operation when CPU core entering C3 state is not
> needed too. Because the chipset will automatically do this operation.
>
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
I've queued up the previous version of your patch with some changes to
comments/subject/changelog made by me for v4.17.
Please see linux-next.
> ---
> arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index dde437f..1cd357b 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> if (c->x86_vendor == X86_VENDOR_INTEL &&
> (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
> flags->bm_control = 0;
> +
> + if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> + /*
> + * on all centaur CPUs, sw need not execute cache flush operation
> + * when entering C3 type State.
> + *
> + * On all Centaur platforms, sw need not execute ARB_DISABLE while
> + * entering C3 type state.
> + */
> + flags->bm_check = 1;
> + flags->bm_control = 0;
> + }
> }
> EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] Delete some unusefull operations for centaur CPU/platform
2018-03-02 4:11 [PATCH] Delete some unusefull operations for centaur CPU/platform David Wang
2018-03-02 11:31 ` Rafael J. Wysocki
@ 2018-03-04 9:31 ` Ingo Molnar
[not found] ` <efc93496e4ba46958b7b09eff54c2ce2@zhaoxin.com>
1 sibling, 1 reply; 7+ messages in thread
From: Ingo Molnar @ 2018-03-04 9:31 UTC (permalink / raw)
To: David Wang
Cc: rjw, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm,
linux-kernel, brucechang, cooperyan, qiyuanwang, benjaminpan,
lukelin, timguo, cobechen, jiangbowang
* David Wang <davidwang@zhaoxin.com> wrote:
> For Centaur CPU, the ucode will make sure that each CPU core can keep cache
> coherency with each other when the CPU core entering to any C state. So the
> cache flush operations when enter C3 is not necessary and will cause large
> C3 enter/exit latency.
> And the bus master disable operation when CPU core entering C3 state is not
> needed too. Because the chipset will automatically do this operation.
>
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> ---
> arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index dde437f..1cd357b 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> if (c->x86_vendor == X86_VENDOR_INTEL &&
> (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
> flags->bm_control = 0;
> +
> + if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> + /*
> + * on all centaur CPUs, sw need not execute cache flush operation
> + * when entering C3 type State.
> + *
> + * On all Centaur platforms, sw need not execute ARB_DISABLE while
> + * entering C3 type state.
> + */
> + flags->bm_check = 1;
> + flags->bm_control = 0;
> + }
Please clean up capitalization and spelling of the comment, and please also
explain the ACPI-idle settings a bit better, i.e. something like:
/*
* On all Centaur CPUs the kernel does not have to
* execute a cache flush operation (WBINVD) when
* entering C3 state.
*
* On all Centaur platforms the kernel does not have to
* disable bus-master arbitration (ARB_DISABLE) when
* entering C3 state.
*/
Also, two questions:
1)
I'm wondering about this logic in acpi_processor_power_verify_c3():
if (pr->flags.bm_check) {
if (!pr->flags.bm_control) {
if (pr->flags.has_cst != 1) {
/* bus mastering control is necessary */
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"C3 support requires BM control\n"));
return;
So ->has_cst is set on Centaur CPUs?
2)
There's this comment in acpi_idle_enter_bm():
/*
* disable bus master
* bm_check implies we need ARB_DIS
* bm_control implies whether we can do ARB_DIS
*
* That leaves a case where bm_check is set and bm_control is
* not set. In that case we cannot do much, we enter C3
* without doing anything.
*/
if (pr->flags.bm_control) {
It says 'bm_check == 1 implies we need ARB_DIS' - but we do the opposite in the
Centaur case? It it me who is confused or the comment?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform
[not found] ` <efc93496e4ba46958b7b09eff54c2ce2@zhaoxin.com>
@ 2018-03-12 8:40 ` Ingo Molnar
2018-03-12 9:27 ` Rafael J. Wysocki
0 siblings, 1 reply; 7+ messages in thread
From: Ingo Molnar @ 2018-03-12 8:40 UTC (permalink / raw)
To: David Wang
Cc: rjw, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm,
linux-kernel, Bruce Chang (VAS), Cooper Yan(BJ-RD),
Qiyuan Wang(BJ-RD), Benjamin Pan, Luke Lin, Tim Guo(BJ-RD),
Cobe Chen(BJ-RD), Jiangbo Wang(BJ-RD)
* David Wang <DavidWang@zhaoxin.com> wrote:
> [David] pr->flags.has_cst means BIOS define valid C state table. And at lease
> define 2 entries. On all centaur platform which support C3, this condition is
> always true.
> [David] Just as the following comment said, we need not execute WBINVD and
> ARB_DISABLE/ARB_ENABLE when entering C3 if bm_check=1 and bm_control=0. This
> logic is valid for all platform not only for Centaur, I think.
Ok, fair enough!
Thanks,
Ingo
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform
2018-03-12 8:40 ` 答复: " Ingo Molnar
@ 2018-03-12 9:27 ` Rafael J. Wysocki
2018-03-12 9:46 ` Ingo Molnar
0 siblings, 1 reply; 7+ messages in thread
From: Rafael J. Wysocki @ 2018-03-12 9:27 UTC (permalink / raw)
To: Ingo Molnar
Cc: David Wang, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm,
linux-kernel, Bruce Chang (VAS), Cooper Yan(BJ-RD),
Qiyuan Wang(BJ-RD), Benjamin Pan, Luke Lin, Tim Guo(BJ-RD),
Cobe Chen(BJ-RD), Jiangbo Wang(BJ-RD)
On Monday, March 12, 2018 9:40:33 AM CET Ingo Molnar wrote:
>
> * David Wang <DavidWang@zhaoxin.com> wrote:
>
> > [David] pr->flags.has_cst means BIOS define valid C state table. And at lease
> > define 2 entries. On all centaur platform which support C3, this condition is
> > always true.
>
> > [David] Just as the following comment said, we need not execute WBINVD and
> > ARB_DISABLE/ARB_ENABLE when entering C3 if bm_check=1 and bm_control=0. This
> > logic is valid for all platform not only for Centaur, I think.
>
> Ok, fair enough!
Well, I still have this one queued up as cpuidle material.
I can drop it if you want to take it instead.
Thanks,
Rafael
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform
2018-03-12 9:27 ` Rafael J. Wysocki
@ 2018-03-12 9:46 ` Ingo Molnar
[not found] ` <0230c32412474e97bf7d2ef45cc64c4d@zhaoxin.com>
0 siblings, 1 reply; 7+ messages in thread
From: Ingo Molnar @ 2018-03-12 9:46 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: David Wang, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm,
linux-kernel, Bruce Chang (VAS), Cooper Yan(BJ-RD),
Qiyuan Wang(BJ-RD), Benjamin Pan, Luke Lin, Tim Guo(BJ-RD),
Cobe Chen(BJ-RD), Jiangbo Wang(BJ-RD)
* Rafael J. Wysocki <rjw@rjwysocki.net> wrote:
> On Monday, March 12, 2018 9:40:33 AM CET Ingo Molnar wrote:
> >
> > * David Wang <DavidWang@zhaoxin.com> wrote:
> >
> > > [David] pr->flags.has_cst means BIOS define valid C state table. And at lease
> > > define 2 entries. On all centaur platform which support C3, this condition is
> > > always true.
> >
> > > [David] Just as the following comment said, we need not execute WBINVD and
> > > ARB_DISABLE/ARB_ENABLE when entering C3 if bm_check=1 and bm_control=0. This
> > > logic is valid for all platform not only for Centaur, I think.
> >
> > Ok, fair enough!
>
> Well, I still have this one queued up as cpuidle material.
>
> I can drop it if you want to take it instead.
No need to drop it, it looks good to me!
Thanks,
Ingo
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: 答复: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform
[not found] ` <0230c32412474e97bf7d2ef45cc64c4d@zhaoxin.com>
@ 2018-03-29 11:03 ` Rafael J. Wysocki
0 siblings, 0 replies; 7+ messages in thread
From: Rafael J. Wysocki @ 2018-03-29 11:03 UTC (permalink / raw)
To: David Wang
Cc: Ingo Molnar, len.brown, pavel, tglx, mingo, hpa, x86, linux-pm,
linux-kernel, Bruce Chang (VAS), Cooper Yan(BJ-RD),
Qiyuan Wang(BJ-RD), Benjamin Pan, Luke Lin, Tim Guo(BJ-RD),
Cobe Chen(BJ-RD), Jiangbo Wang(BJ-RD)
On Wednesday, March 28, 2018 11:21:15 AM CEST David Wang wrote:
> Dear Rafael,
>
> After disscusion with engineer from Centaur, the orginal patch maybe not safe for some older Centaur CPU/platform. So, I want to use another patch like the following:
OK
I will drop the previous one, no problem.
Please resumbit the new one on top of the Linus' tree.
Thanks!
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 6c74dec..d92a7f3 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -52,17 +52,15 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
> (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
> flags->bm_control = 0;
>
> - if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> - /*
> - * On all Centaur CPUs, software need not flush the CPU caches
> - * when entering C3-type C-states.
> - *
> - * On all Centaur platforms, software need not disable bus
> - * master arbitration when entering C3-type C-states.
> - */
> - flags->bm_check = 1;
> - flags->bm_control = 0;
> - }
> + /*
> + * For all recent Centaur CPUs, the ucode will make sure that each core can keep
> + * cache coherence with each other while entering C3 type state.
> + * So, set bm_check to 1 to indicate that the kernel need not execute a cache
> + * flush operation (WBINVD) when entering C3 type state.
> + */
> + if (c->x86_vendor == X86_VENDOR_CENTAUR &&
> + (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && c->x86_mask>=0x0e)))
> + flags->bm_check = 1;
> }
> EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
> Can you help to drop the orignal patch you queued up to the linux-next?
> Thank you.
>
>
> David
>
> ________________________________
> 发件人: Ingo Molnar <mingo.kernel.org@gmail.com> 代表 Ingo Molnar <mingo@kernel.org>
> 发送时间: 2018年3月12日 17:46:09
> 收件人: Rafael J. Wysocki
> 抄送: David Wang; len.brown@intel.com; pavel@ucw.cz; tglx@linutronix.de; mingo@redhat.com; hpa@zytor.com; x86@kernel.org; linux-pm@kernel.org; linux-kernel@vger.kernel.org; Bruce Chang (VAS); Cooper Yan(BJ-RD); Qiyuan Wang(BJ-RD); Benjamin Pan; Luke Lin; Tim Guo(BJ-RD); Cobe Chen(BJ-RD); Jiangbo Wang(BJ-RD)
> 主题: Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform
>
>
> * Rafael J. Wysocki <rjw@rjwysocki.net> wrote:
>
> > On Monday, March 12, 2018 9:40:33 AM CET Ingo Molnar wrote:
> > >
> > > * David Wang <DavidWang@zhaoxin.com> wrote:
> > >
> > > > [David] pr->flags.has_cst means BIOS define valid C state table. And at lease
> > > > define 2 entries. On all centaur platform which support C3, this condition is
> > > > always true.
> > >
> > > > [David] Just as the following comment said, we need not execute WBINVD and
> > > > ARB_DISABLE/ARB_ENABLE when entering C3 if bm_check=1 and bm_control=0. This
> > > > logic is valid for all platform not only for Centaur, I think.
> > >
> > > Ok, fair enough!
> >
> > Well, I still have this one queued up as cpuidle material.
> >
> > I can drop it if you want to take it instead.
>
> No need to drop it, it looks good to me!
>
> Thanks,
>
> Ingo
>
^ permalink raw reply [flat|nested] 7+ messages in thread
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2018-03-02 4:11 [PATCH] Delete some unusefull operations for centaur CPU/platform David Wang
2018-03-02 11:31 ` Rafael J. Wysocki
2018-03-04 9:31 ` Ingo Molnar
[not found] ` <efc93496e4ba46958b7b09eff54c2ce2@zhaoxin.com>
2018-03-12 8:40 ` 答复: " Ingo Molnar
2018-03-12 9:27 ` Rafael J. Wysocki
2018-03-12 9:46 ` Ingo Molnar
[not found] ` <0230c32412474e97bf7d2ef45cc64c4d@zhaoxin.com>
2018-03-29 11:03 ` 答复: " Rafael J. Wysocki
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