From: <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Paul Burton" <paulburton@kernel.org>,
"Ralf Baechle" <ralf@linux-mips.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Rob Herring" <robh+dt@kernel.org>,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
"Thomas Bogendoerfer" <tbogendoerfer@suse.de>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Alexander Lobakin" <alobakin@dlink.ru>,
"Huacai Chen" <chenhc@lemote.com>,
"Cedric Hombourger" <Cedric_Hombourger@mentor.com>,
"René van Dorst" <opensource@vdorst.com>,
"Ard Biesheuvel" <ardb@kernel.org>,
"Jessica Yu" <jeyu@kernel.org>,
"Masahiro Yamada" <masahiroy@kernel.org>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support
Date: Wed, 6 May 2020 20:42:25 +0300 [thread overview]
Message-ID: <20200506174238.15385-8-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200506174238.15385-1-Sergey.Semin@baikalelectronics.ru>
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue
exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features
and system level features like up to six P5600 calculation cores, CM2
with L2 cache, IOCU/IOMMU (though might be unused depending on the
system-specific IP core configuration), GIC, CPC, virtualisation module,
eJTAG and PDtrace.
As being MIPS32 Release 5 based core it provides all the features
available by the CPU_MIPS32_R5 config, while adding a few more like
UCA attribute support, availability of CPU-freq (by means of L2/CM
clock ratio setting), EI/VI GIC modes detection at runtime.
In addition to this if P5600 architecture is enabled modern GNU GCC
provides a specific tuning for P5600 processors with respect to the
classic MIPS32 Release 5. First of all branch-likely avoidance is
activated only when the code is compiled with the speed optimization
(avoidance is always enabled for the pure MIPS32 Release 5
architecture). Secondly the madd/msub avoidance is enabled since
madd/msub utilization isn't profitable due to overhead of getting the
result out of the HI/LO registers. Multiply-accumulate instructions are
activated and utilized together with the necessary code reorder when
multiply-add/multiply-subtract statements are met. Finally load/store
bonding is activated by default. All of these optimizations may make
the code relatively faster than if just MIP32 release 5 architecture
was requested.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-pm@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
arch/mips/Kconfig | 38 +++++++++++++++++++++++++++-----
arch/mips/Makefile | 1 +
arch/mips/include/asm/vermagic.h | 2 ++
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 55c3dbfea336..e3b780a389a9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1665,6 +1665,28 @@ config CPU_MIPS64_R6
family, are based on a MIPS64r6 processor. If you own an older
processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
+config CPU_P5600
+ bool "MIPS Warrior P5600"
+ depends on SYS_HAS_CPU_P5600
+ select CPU_HAS_PREFETCH
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ select CPU_SUPPORTS_MSA
+ select CPU_SUPPORTS_UNCACHED_ACCELERATED
+ select CPU_SUPPORTS_CPUFREQ
+ select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
+ select HAVE_KVM
+ select MIPS_O32_FP64_SUPPORT
+ help
+ Choose this option to build a kernel for MIPS Warrior P5600 CPU.
+ It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
+ MMU with two-levels TLB, UCA, MSA, MDU core level features and system
+ level features like up to six P5600 calculation cores, CM2 with L2
+ cache, IOCU/IOMMU (though might be unused depending on the system-
+ specific IP core configuration), GIC, CPC, virtualisation module,
+ eJTAG and PDtrace.
+
config CPU_R3000
bool "R3000"
depends on SYS_HAS_CPU_R3000
@@ -1841,7 +1863,8 @@ endchoice
config CPU_MIPS32_3_5_FEATURES
bool "MIPS32 Release 3.5 Features"
depends on SYS_HAS_CPU_MIPS32_R3_5
- depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6
+ depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
+ CPU_P5600
help
Choose this option to build a kernel for release 2 or later of the
MIPS32 architecture including features from the 3.5 release such as
@@ -1861,7 +1884,7 @@ config CPU_MIPS32_3_5_EVA
config CPU_MIPS32_R5_FEATURES
bool "MIPS32 Release 5 Features"
depends on SYS_HAS_CPU_MIPS32_R5
- depends on CPU_MIPS32_R2 || CPU_MIPS32_R5
+ depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
help
Choose this option to build a kernel for release 2 or later of the
MIPS32 architecture including features from release 5 such as
@@ -2016,6 +2039,10 @@ config SYS_HAS_CPU_MIPS64_R6
bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
+config SYS_HAS_CPU_P5600
+ bool
+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
+
config SYS_HAS_CPU_R3000
bool
@@ -2100,7 +2127,7 @@ endmenu
config CPU_MIPS32
bool
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
- CPU_MIPS32_R6
+ CPU_MIPS32_R6 || CPU_P5600
config CPU_MIPS64
bool
@@ -2122,7 +2149,7 @@ config CPU_MIPSR2
config CPU_MIPSR5
bool
- default y if CPU_MIPS32_R5
+ default y if CPU_MIPS32_R5 || CPU_P5600
select CPU_HAS_RIXI
select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM
@@ -2733,7 +2760,8 @@ config RELOCATABLE
bool "Relocatable kernel"
depends on SYS_SUPPORTS_RELOCATABLE
depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R5 || \
- CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC
+ CPU_MIPS32_R6 || CPU_MIPS64_R6 || CPU_P5600 || \
+ CAVIUM_OCTEON_SOC
help
This builds a kernel image that retains relocation information
so it can be loaded someplace besides the default 1MB.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9172fb0f630b..264dead560f4 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -176,6 +176,7 @@ cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
+cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \
-Wa,--trap
diff --git a/arch/mips/include/asm/vermagic.h b/arch/mips/include/asm/vermagic.h
index 5a0e739f597a..d03f97350f91 100644
--- a/arch/mips/include/asm/vermagic.h
+++ b/arch/mips/include/asm/vermagic.h
@@ -48,6 +48,8 @@
#define MODULE_PROC_FAMILY "LOONGSON64 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
+#elif defined CONFIG_CPU_P5600
+#define MODULE_PROC_FAMILY "P5600 "
#elif defined CONFIG_CPU_XLR
#define MODULE_PROC_FAMILY "XLR "
#elif defined CONFIG_CPU_XLP
--
2.25.1
next prev parent reply other threads:[~2020-05-06 17:44 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 12:46 [PATCH 00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 00/20] " Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:04 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC Sergey.Semin
2020-05-06 17:55 ` Sam Ravnborg
2020-05-06 19:20 ` Serge Semin
2020-05-06 19:26 ` Sam Ravnborg
2020-05-06 20:18 ` Serge Semin
2020-05-14 18:13 ` Serge Semin
2020-05-14 18:31 ` Rob Herring
2020-05-06 17:42 ` [PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR Sergey.Semin
2020-05-07 11:10 ` Thomas Bogendoerfer
2020-05-07 21:32 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:38 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 06/20] mips: Add MIPS32 Release 5 support Sergey.Semin
2020-05-08 13:30 ` Thomas Bogendoerfer
2020-05-10 22:05 ` Serge Semin
2020-05-06 17:42 ` Sergey.Semin [this message]
2020-05-07 11:17 ` [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support Thomas Bogendoerfer
2020-05-07 21:19 ` Serge Semin
2020-05-08 9:32 ` Thomas Bogendoerfer
2020-05-08 12:21 ` Thomas Bogendoerfer
2020-05-10 22:09 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Sergey.Semin
2020-05-08 13:28 ` Thomas Bogendoerfer
2020-05-10 23:59 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 09/20] mips: Add CP0 Write Merge config support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 11/20] mips: MAAR: Use more precise address mask Sergey.Semin
2020-05-07 11:09 ` Thomas Bogendoerfer
2020-05-07 19:13 ` Serge Semin
2020-05-08 9:22 ` Thomas Bogendoerfer
2020-05-10 22:13 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 12/20] mips: MAAR: Add XPA mode support Sergey.Semin
2020-05-19 15:42 ` Thomas Bogendoerfer
2020-05-20 11:30 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Sergey.Semin
2020-05-06 18:16 ` Sergei Shtylyov
2020-05-06 19:52 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment Sergey.Semin
2020-05-08 12:15 ` Jiaxun Yang
2020-05-06 17:42 ` [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled Sergey.Semin
2020-05-08 15:41 ` Thomas Bogendoerfer
2020-05-11 13:31 ` Serge Semin
2020-05-15 7:48 ` Serge Semin
2020-05-15 21:06 ` Thomas Bogendoerfer
2020-05-16 11:55 ` Serge Semin
2020-05-18 13:48 ` Serge Semin
2020-05-18 16:32 ` Thomas Bogendoerfer
2020-05-18 20:57 ` Serge Semin
2020-05-19 15:50 ` Thomas Bogendoerfer
2020-05-20 11:59 ` Serge Semin
2020-05-20 14:03 ` Serge Semin
2020-05-20 18:40 ` Thomas Bogendoerfer
2020-05-20 21:13 ` Serge Semin
2020-05-20 12:12 ` Serge Semin
2020-05-20 12:21 ` Serge Semin
2020-05-20 13:38 ` Thomas Bogendoerfer
2020-05-20 13:48 ` Serge Semin
2020-05-20 18:30 ` Thomas Bogendoerfer
2020-05-20 21:12 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Sergey.Semin
2020-05-08 15:40 ` Thomas Bogendoerfer
2020-05-11 0:34 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting Sergey.Semin
2020-05-15 15:58 ` Rafael J. Wysocki
2020-05-16 12:52 ` Serge Semin
2020-05-18 7:41 ` Viresh Kumar
2020-05-18 9:53 ` Rafael J. Wysocki
2020-05-18 10:11 ` Viresh Kumar
2020-05-18 10:22 ` Rafael J. Wysocki
2020-05-18 10:24 ` Viresh Kumar
2020-05-18 10:31 ` Serge Semin
2020-05-18 10:41 ` Rafael J. Wysocki
2020-05-18 10:46 ` Serge Semin
2020-05-18 10:51 ` Rafael J. Wysocki
2020-05-18 10:56 ` Serge Semin
2020-05-18 11:05 ` Rafael J. Wysocki
2020-05-19 1:50 ` Xiongfeng Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200506174238.15385-8-Sergey.Semin@baikalelectronics.ru \
--to=sergey.semin@baikalelectronics.ru \
--cc=Alexey.Malahov@baikalelectronics.ru \
--cc=Cedric_Hombourger@mentor.com \
--cc=alobakin@dlink.ru \
--cc=ardb@kernel.org \
--cc=arnd@arndb.de \
--cc=chenhc@lemote.com \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=jeyu@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=masahiroy@kernel.org \
--cc=opensource@vdorst.com \
--cc=paulburton@kernel.org \
--cc=ralf@linux-mips.org \
--cc=robh+dt@kernel.org \
--cc=tbogendoerfer@suse.de \
--cc=tsbogend@alpha.franken.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).