From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>, Arnd Bergmann <arnd@arndb.de>,
Rob Herring <robh+dt@kernel.org>, <linux-pm@vger.kernel.org>,
<devicetree@vger.kernel.org>, Zhou Yanjie <zhouyanjie@zoho.com>,
Paul Cercueil <paul@crapouillou.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
<linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 11/20] mips: MAAR: Use more precise address mask
Date: Mon, 11 May 2020 01:13:44 +0300 [thread overview]
Message-ID: <20200510221344.kixpbwy2kcxf62ie@mobilestation> (raw)
In-Reply-To: <20200508092236.GA9085@alpha.franken.de>
On Fri, May 08, 2020 at 11:22:36AM +0200, Thomas Bogendoerfer wrote:
> On Thu, May 07, 2020 at 10:13:37PM +0300, Serge Semin wrote:
> > On Thu, May 07, 2020 at 01:09:51PM +0200, Thomas Bogendoerfer wrote:
> > > On Wed, May 06, 2020 at 08:42:29PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> > > > From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > > >
> > > > Indeed according to the P5600/P6000 manual the MAAR pair register
> > > > address field either takes [12:31] bits for 32-bits non-XPA systems
> > > > and [12:35] otherwise. In any case the current address mask is just
> > > > wrong for 64-bit and 32-bits XPA chips. So lets extend it to 39-bits
> > > > value. This shall cover the 64-bits architecture and systems with XPA
> > > > enabled, and won't cause any problem for non-XPA 32-bit systems, since
> > > > the value will be just truncated when written to the 32-bits register.
> > >
> > > according to MIPS32 Priveleged Resoure Architecture Rev. 6.02
> > > ADDR spans from bit 12 to bit 55. So your patch fits only for P5600.
> >
> > > Does the wider mask cause any problems ?
> >
> > No, it won't. Bits written to the [40:62] range will be just ignored,
> > while reading from there should return zeros. Setting GENMASK_ULL(55, 12)
> > would also work. Though this solution is a bit workarounding because
> > MIPS_MAAR_ADDR wouldn't reflect the real mask of the ADDR field. Something
> > like the next macro would work better:
> >
> > +#define MIPS_MAAR_ADDR \
> > +({ \
> > + u64 __mask; \
> > + \
> > + if (cpu_has_lpa && read_c0_pagegrain() & PG_ELPA) { \
> > + __mask = GENMASK_ULL(55, 12); \
> > + else \
> > + __mask = GENMASK_ULL(31, 12); \
> > + \
> > + __mask; \
> > +})
>
> that looks horrible.
>
> > What do you think? What is better: the macro above or setting
> > GENMASK_ULL(55, 12)?
>
> just that one ;-)
Agreed. I'll fix it in v3.
-Sergey
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2020-05-10 22:13 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-06 12:46 [PATCH 00/22] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 00/20] " Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:04 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller Sergey.Semin
2020-05-14 15:09 ` Rob Herring
2020-05-14 18:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC Sergey.Semin
2020-05-06 17:55 ` Sam Ravnborg
2020-05-06 19:20 ` Serge Semin
2020-05-06 19:26 ` Sam Ravnborg
2020-05-06 20:18 ` Serge Semin
2020-05-14 18:13 ` Serge Semin
2020-05-14 18:31 ` Rob Herring
2020-05-06 17:42 ` [PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR Sergey.Semin
2020-05-07 11:10 ` Thomas Bogendoerfer
2020-05-07 21:32 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:38 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 06/20] mips: Add MIPS32 Release 5 support Sergey.Semin
2020-05-08 13:30 ` Thomas Bogendoerfer
2020-05-10 22:05 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 07/20] mips: Add MIPS Warrior P5600 support Sergey.Semin
2020-05-07 11:17 ` Thomas Bogendoerfer
2020-05-07 21:19 ` Serge Semin
2020-05-08 9:32 ` Thomas Bogendoerfer
2020-05-08 12:21 ` Thomas Bogendoerfer
2020-05-10 22:09 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Sergey.Semin
2020-05-08 13:28 ` Thomas Bogendoerfer
2020-05-10 23:59 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 09/20] mips: Add CP0 Write Merge config support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 11/20] mips: MAAR: Use more precise address mask Sergey.Semin
2020-05-07 11:09 ` Thomas Bogendoerfer
2020-05-07 19:13 ` Serge Semin
2020-05-08 9:22 ` Thomas Bogendoerfer
2020-05-10 22:13 ` Serge Semin [this message]
2020-05-06 17:42 ` [PATCH v2 12/20] mips: MAAR: Add XPA mode support Sergey.Semin
2020-05-19 15:42 ` Thomas Bogendoerfer
2020-05-20 11:30 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout Sergey.Semin
2020-05-06 18:16 ` Sergei Shtylyov
2020-05-06 19:52 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support Sergey.Semin
2020-05-06 17:42 ` [PATCH v2 17/20] mips: Add udelay lpj numbers adjustment Sergey.Semin
2020-05-08 12:15 ` Jiaxun Yang
2020-05-06 17:42 ` [PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled Sergey.Semin
2020-05-08 15:41 ` Thomas Bogendoerfer
2020-05-11 13:31 ` Serge Semin
2020-05-15 7:48 ` Serge Semin
2020-05-15 21:06 ` Thomas Bogendoerfer
2020-05-16 11:55 ` Serge Semin
2020-05-18 13:48 ` Serge Semin
2020-05-18 16:32 ` Thomas Bogendoerfer
2020-05-18 20:57 ` Serge Semin
2020-05-19 15:50 ` Thomas Bogendoerfer
2020-05-20 11:59 ` Serge Semin
2020-05-20 14:03 ` Serge Semin
2020-05-20 18:40 ` Thomas Bogendoerfer
2020-05-20 21:13 ` Serge Semin
2020-05-20 12:12 ` Serge Semin
2020-05-20 12:21 ` Serge Semin
2020-05-20 13:38 ` Thomas Bogendoerfer
2020-05-20 13:48 ` Serge Semin
2020-05-20 18:30 ` Thomas Bogendoerfer
2020-05-20 21:12 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Sergey.Semin
2020-05-08 15:40 ` Thomas Bogendoerfer
2020-05-11 0:34 ` Serge Semin
2020-05-06 17:42 ` [PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting Sergey.Semin
2020-05-15 15:58 ` Rafael J. Wysocki
2020-05-16 12:52 ` Serge Semin
2020-05-18 7:41 ` Viresh Kumar
2020-05-18 9:53 ` Rafael J. Wysocki
2020-05-18 10:11 ` Viresh Kumar
2020-05-18 10:22 ` Rafael J. Wysocki
2020-05-18 10:24 ` Viresh Kumar
2020-05-18 10:31 ` Serge Semin
2020-05-18 10:41 ` Rafael J. Wysocki
2020-05-18 10:46 ` Serge Semin
2020-05-18 10:51 ` Rafael J. Wysocki
2020-05-18 10:56 ` Serge Semin
2020-05-18 11:05 ` Rafael J. Wysocki
2020-05-19 1:50 ` Xiongfeng Wang
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