[PATCH v3 0/8] arm: Base support for Renesas RZN1D-DB Board

[PATCH v3 0/8] arm: Base support for Renesas RZN1D-DB Board

[Michel Pollet]

This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support, pinctrl, clock architecture and quite
a few others.

Thanks for the comments on the previous version!

v3:
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
 + Kept renesas,rzn1 as a family/generic for this family.
 + Fixed a couple of the commit messages.
 + Added Geert's Reviewed-By where appropriate.
v2: 
 + Fixes for suggestions by Simon Horman
 + Fixes for suggestions by Rob Herring
 + Fixes for suggestions by Geert Uytterhoeven
 + Removed the mach file
 + Added a MFD base for the sysctrl block
 + Added a regmap based sub driver for the reboot handler
 + Renamed the files to match shmobile conventions
 + Adapted the compatible= strings to reflect 'family' vs 'part'
   distinction.
 + Removed the sysctrl.h file entirelly. 
 + Fixed every warnings from the DTC compiler on W=12 mode.
 + Split the device-tree patches from the code.

Michel Pollet (8):
  DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node
  DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver
  DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board
  reset: Renesas RZ/N1 reboot driver
  arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig
  DT: arm: Add Renesas RZ/N1 SoC base device tree file
  DT: arm: Add Renesas RZN1D-DB Board base file
  DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

 Documentation/devicetree/bindings/arm/shmobile.txt |   7 +-
 .../bindings/mfd/renesas,rzn1-sysctrl.txt          |  19 ++++
 .../bindings/power/renesas,rzn1-reboot.txt         |  20 ++++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts        |  26 +++++
 arch/arm/boot/dts/r9a06g0xx.dtsi                   |  96 +++++++++++++++++++
 arch/arm/mach-shmobile/Kconfig                     |   5 +
 drivers/power/reset/Kconfig                        |   7 ++
 drivers/power/reset/Makefile                       |   1 +
 drivers/power/reset/rzn1-reboot.c                  | 105 +++++++++++++++++++++
 10 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
 create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
 create mode 100644 drivers/power/reset/rzn1-reboot.c

-- 
2.7.4

[PATCH v3 1/8] DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
system controller. This documents the node used to encapsulate
it's sub drivers.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 .../devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt  | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt

diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt b/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
new file mode 100644
index 0000000..1dbfdaf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
@@ -0,0 +1,19 @@
+DT bindings for the Renesas RZ/N1 System Controller
+
+== System Controller Node ==
+
+The system controller node currently only hosts a single sub-node to handle
+the rebooting of the CPU. Eventually it will host the clock driver, SMP
+start handler, watchdog etc.
+
+See renesas,rzn1-reboot.txt for further details.
+
+Bindings:
++ Required:
+	compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+
+Example:
+	sysctrl: sysctrl@4000c000 {
+		compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+		reg = <0x4000c000 0x1000>;
+	};
-- 
2.7.4

[PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 .../bindings/power/renesas,rzn1-reboot.txt           | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt

diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
new file mode 100644
index 0000000..f592769
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
@@ -0,0 +1,20 @@
+DT bindings for the Renesas RZ/N1 Reboot Driver
+
+== Reboot Driver Node ==
+
+The reboot driver is always a subnode of the system controller node, see
+renesas,rzn1-sysctrl.txt for details.
+
+Bindings:
++ Required:
+	compatible = "renesas,rzn1-reboot";
+
+Example:
+	sysctrl: sysctrl@4000c000 {
+		compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
+		reg = <0x4000c000 0x1000>;
+
+		reboot {
+			compatible = "renesas,rzn1-reboot";
+		};
+	};
-- 
2.7.4

[PATCH v3 3/8] DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board

[Michel Pollet]

This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D-DB
board.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index d3d1df9..52368fc 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -47,7 +47,10 @@ SoCs:
     compatible = "renesas,r8a77980"
   - R-Car D3 (R8A77995)
     compatible = "renesas,r8a77995"
-
+  - RZ/N1 Family (R9A06G032 & R9A06G033)
+    compatible = "renesas,rzn1"
+  - RZ/N1D (R9A06G032)
+    compatible = "renesas,r9a06g032", "renesas,rzn1"
 
 Boards:
 
@@ -104,6 +107,8 @@ Boards:
     compatible = "renesas,porter", "renesas,r8a7791"
   - RSKRZA1 (YR0K77210C000BE)
     compatible = "renesas,rskrza1", "renesas,r7s72100"
+  - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+    compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1"
   - Salvator-X (RTP0RC7795SIPB0010S)
     compatible = "renesas,salvator-x", "renesas,r8a7795"
   - Salvator-X (RTP0RC7796SIPB0011S)
-- 
2.7.4

[PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 drivers/power/reset/Kconfig       |   7 +++
 drivers/power/reset/Makefile      |   1 +
 drivers/power/reset/rzn1-reboot.c | 105 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 113 insertions(+)
 create mode 100644 drivers/power/reset/rzn1-reboot.c

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index df58fc8..1416d88 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -144,6 +144,13 @@ config POWER_RESET_RESTART
 	  Instead they restart, and u-boot holds the SoC until the
 	  user presses a key. u-boot then boots into Linux.
 
+config POWER_RESET_RZN1
+	bool "Renesas RZ/N1 reboot driver"
+	depends on ARCH_RZN1
+	help
+	  This driver allows rebooting the CA7 cores of the
+	  Renesas RZ/N1 Family of SoC (Part # R9A06G0xx).
+
 config POWER_RESET_ST
 	bool "ST restart driver"
 	depends on ARCH_STI
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 7778c74..bad9702 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
 obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
 obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
 obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+obj-$(CONFIG_POWER_RESET_RZN1) += rzn1-reboot.o
 obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
 obj-$(CONFIG_POWER_RESET_VERSATILE) += arm-versatile-reboot.o
 obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
diff --git a/drivers/power/reset/rzn1-reboot.c b/drivers/power/reset/rzn1-reboot.c
new file mode 100644
index 0000000..54fdd81
--- /dev/null
+++ b/drivers/power/reset/rzn1-reboot.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 reboot driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ * Derived from zx-reboot.c
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+/* Definitions from the SDK rzn1-sysctrl.h autogenerated file */
+#define RZN1_SYSCTRL_REG_RSTEN			0x120
+#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN		0
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN		1
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_EN_MASK		0x6
+#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN		3
+#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN		4
+#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN		5
+#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN			6
+#define RZN1_SYSCTRL_REG_RSTCTRL		0x198
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ		1
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDA7RST_REQ_MASK	0x6
+#define RZN1_SYSCTRL_REG_RSTCTRL_WDM3RST_REQ		3
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3LOCKUPRST_REQ	4
+#define RZN1_SYSCTRL_REG_RSTCTRL_CM3SYSRESET_REQ	5
+#define RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ		6
+
+static struct regmap *sysctrl;
+
+static int rzn1_reboot_handler(struct notifier_block *this,
+			      unsigned long mode, void *cmd)
+{
+	regmap_write_bits(sysctrl,
+			RZN1_SYSCTRL_REG_RSTEN,
+			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+				BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN),
+			BIT(RZN1_SYSCTRL_REG_RSTEN_SWRST_EN) |
+				BIT(RZN1_SYSCTRL_REG_RSTEN_MRESET_EN));
+	regmap_write_bits(sysctrl,
+			RZN1_SYSCTRL_REG_RSTCTRL,
+			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ),
+			BIT(RZN1_SYSCTRL_REG_RSTCTRL_SWRST_REQ));
+
+	mdelay(50);
+	pr_emerg("Unable to restart system\n");
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block rzn1_reboot_nb = {
+	.notifier_call = rzn1_reboot_handler,
+	.priority = 128,
+};
+
+static int rzn1_reboot_probe(struct platform_device *pdev)
+{
+	int err;
+	struct device *parent;
+
+	parent = pdev->dev.parent;
+	if (!parent || !parent->of_node)
+		dev_err(&pdev->dev, "couldn't find sysctrl node\n");
+		return -ENODEV;
+	}
+	sysctrl = syscon_node_to_regmap(parent->of_node);
+	if (IS_ERR(sysctrl)) {
+		dev_err(&pdev->dev, "couldn't find find regmap\n");
+		return PTR_ERR(sysctrl);
+	}
+	err = register_restart_handler(&rzn1_reboot_nb);
+	if (err) {
+		dev_err(&pdev->dev, "register restart handler failed(err=%d)\n",
+			err);
+	}
+
+	return err;
+}
+
+static const struct of_device_id rzn1_reboot_of_match[] = {
+	{ .compatible = "renesas,rzn1-reboot" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
+
+static struct platform_driver rzn1_reboot_driver = {
+	.probe = rzn1_reboot_probe,
+	.driver = {
+		.name = "rzn1-reboot",
+		.of_match_table = rzn1_reboot_of_match,
+	},
+};
+module_platform_driver(rzn1_reboot_driver);
+
+MODULE_DESCRIPTION("RZ/N1 reboot driver");
+MODULE_AUTHOR("Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

[PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig

[Michel Pollet]

Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
the Renesas SoC collection.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/mach-shmobile/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 280e731..221fbcb 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -110,6 +110,11 @@ config ARCH_R8A7794
 	bool "R-Car E2 (R8A77940)"
 	select ARCH_RCAR_GEN2
 
+config ARCH_RZN1
+	bool "RZ/N1 (R9A06G0xx) Family"
+	select ARM_AMBA
+	select CPU_V7
+
 config ARCH_SH73A0
 	bool "SH-Mobile AG5 (R8A73A00)"
 	select ARCH_RMOBILE
-- 
2.7.4

[PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[Michel Pollet]

This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
bare bone support.

This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g0xx.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi

diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi b/arch/arm/boot/dts/r9a06g0xx.dtsi
new file mode 100644
index 0000000..c6eeee3
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,rzn1";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+		};
+	};
+	clocks {
+		/*
+		 * this is fixed clock for now,
+		 * until the clock driver is merged
+		 */
+		clkuarts: clkuarts {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <47619047>;
+		};
+	};
+	arch-timer {
+		compatible = "arm,cortex-a7-timer",
+			     "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		arm,cpu-registers-not-fw-configured;
+		interrupts =
+			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+				IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+				IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+				IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+				IRQ_TYPE_LEVEL_LOW)>;
+	};
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		gic: gic@44101000 {
+			compatible = "arm,cortex-a7-gic", "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x44101000 0x1000>, /* Distributer */
+			      <0x44102000 0x2000>, /* CPU interface */
+			      <0x44104000 0x2000>, /* Virt interface control */
+			      <0x44106000 0x2000>; /* Virt CPU interface */
+			interrupts =
+				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+		sysctrl: sysctrl@4000c000 {
+			compatible = "renesas,rzn1-sysctrl", "syscon",
+					"simple-mfd";
+			reg = <0x4000c000 0x1000>;
+
+			reboot {
+				compatible = "renesas,rzn1-reboot";
+			};
+		};
+		uart0: serial@40060000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x40060000 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&clkuarts>;
+			clock-names = "baudclk";
+			status = "disabled";
+		};
+	};
+};
-- 
2.7.4

[PATCH v3 7/8] DT: arm: Add Renesas RZN1D-DB Board base file

[Michel Pollet]

This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 0000000..a462b1a
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g0xx.dtsi"
+
+/ {
+	model = "RZN1D-DB Board";
+	compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+	aliases {
+		serial0 = &uart0;
+	};
+};
+&uart0 {
+	status = "okay";
+};
-- 
2.7.4

[PATCH v3 8/8] DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

[Michel Pollet]

This adds the newly added board to the Renesas built target

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8164c12..1849228 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -806,6 +806,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
 	r8a7793-gose.dtb \
 	r8a7794-alt.dtb \
 	r8a7794-silk.dtb \
+	r9a06g032-rzn1d400-db.dtb \
 	sh73a0-kzm9g.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1108-evb.dtb \
-- 
2.7.4

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[jacopo mondi]

[-- Attachment #1: Type: text/plain, Size: 4679 bytes --]

Hi Michel

The subject of all your patches for arch/arm should start with:

ARM: dts:

A git log on that directory clearly shows that's the preferred one.

I would also say that you are missing a symbol definition in
arch/arm/mach-shmobile/Kconfig
(even if you got rid of any board file)

I would expect a symbol to select in menuconfig, with your
dependencies listed there (ie, the serial interface driver)

Something like this (I left the 'xx' out from the part name on purpose)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 280e731..9a519330 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -114,4 +114,8 @@ config ARCH_SH73A0
        bool "SH-Mobile AG5 (R8A73A00)"
        select ARCH_RMOBILE
        select RENESAS_INTC_IRQPIN
+
+config ARCH_R9A06G0
+       bool "RZ/N1 (R9A06G0)"
+       select SERIAL_8250_DW
 endif

But please wait for others (preferibly Geert or Simon) to confim this.

On Thu, Mar 29, 2018 at 08:47:02AM +0100, Michel Pollet wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r9a06g0xx.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
>
> diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi b/arch/arm/boot/dts/r9a06g0xx.dtsi
> new file mode 100644
> index 0000000..c6eeee3
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "renesas,rzn1";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <0>;
> +		};
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a7";
> +			reg = <1>;
> +		};
> +	};

I see you don't like empy lines, that's fine, it is not a strict
requiremen afaik, but I find a few empty lines here and there more
redable, expecially if the file is going to grow, as it will be.


> +	clocks {
> +		/*
> +		 * this is fixed clock for now,
> +		 * until the clock driver is merged
> +		 */
> +		clkuarts: clkuarts {

You can remove the node lable if it's the same as the node name afaik

> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <47619047>;
> +		};
> +	};

Grouping clock nodes under a "clocks" one is now deprecated.

Please see, ie.
"ARM: dts: r7s72100: stop grouping clocks under a "clocks" subnode"

Thanks
   j

> +	arch-timer {
> +		compatible = "arm,cortex-a7-timer",
> +			     "arm,armv7-timer";
> +		interrupt-parent = <&gic>;
> +		arm,cpu-registers-not-fw-configured;
> +		interrupts =
> +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> +				IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> +				IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> +				IRQ_TYPE_LEVEL_LOW)>,
> +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> +				IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		interrupt-parent = <&gic>;
> +		ranges;
> +
> +		gic: gic@44101000 {
> +			compatible = "arm,cortex-a7-gic", "arm,gic-400";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0x44101000 0x1000>, /* Distributer */
> +			      <0x44102000 0x2000>, /* CPU interface */
> +			      <0x44104000 0x2000>, /* Virt interface control */
> +			      <0x44106000 0x2000>; /* Virt CPU interface */
> +			interrupts =
> +				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> +					IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +		sysctrl: sysctrl@4000c000 {
> +			compatible = "renesas,rzn1-sysctrl", "syscon",
> +					"simple-mfd";
> +			reg = <0x4000c000 0x1000>;
> +
> +			reboot {
> +				compatible = "renesas,rzn1-reboot";
> +			};
> +		};
> +		uart0: serial@40060000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x40060000 0x400>;
> +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&clkuarts>;
> +			clock-names = "baudclk";
> +			status = "disabled";
> +		};
> +	};
> +};
> --
> 2.7.4
>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

RE: [PATCH v3 4/8] reset: Renesas RZ/N1 reboot driver

[Michel Pollet]

On 29 March 2018 08:47, I messed up:
[snip]
>
> The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver to reboot
> the Cortex-A7 cores. This driver is a sub driver of the sysctrl MFD.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  drivers/power/reset/Kconfig       |   7 +++
>  drivers/power/reset/Makefile      |   1 +
>  drivers/power/reset/rzn1-reboot.c | 105
[snip]
> +
> +parent = pdev->dev.parent;
> +if (!parent || !parent->of_node)

Not sure what went on when I had all the patches loaded in the editor before sending, but I've deleted a brace here. Will be fixed in v4... :/

Michel


> +dev_err(&pdev->dev, "couldn't find sysctrl node\n");
> +return -ENODEV;
> +}
> +sysctrl = syscon_node_to_regmap(parent->of_node);
> +if (IS_ERR(sysctrl)) {
> +dev_err(&pdev->dev, "couldn't find find regmap\n");
> +return PTR_ERR(sysctrl);
> +}
> +err = register_restart_handler(&rzn1_reboot_nb);
> +if (err) {
> +dev_err(&pdev->dev, "register restart handler
> failed(err=%d)\n",
> +err);
> +}
> +
> +return err;
> +}
> +
> +static const struct of_device_id rzn1_reboot_of_match[] = {
> +{ .compatible = "renesas,rzn1-reboot" },
> +{}
> +};
> +MODULE_DEVICE_TABLE(of, rzn1_reboot_of_match);
> +
> +static struct platform_driver rzn1_reboot_driver = {
> +.probe = rzn1_reboot_probe,
> +.driver = {
> +.name = "rzn1-reboot",
> +.of_match_table = rzn1_reboot_of_match,
> +},
> +};
> +module_platform_driver(rzn1_reboot_driver);
> +
> +MODULE_DESCRIPTION("RZ/N1 reboot driver");
> MODULE_AUTHOR("Michel Pollet
> +<michel.pollet@bp.renesas.com>, <buserror@gmail.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig

[Simon Horman]

On Thu, Mar 29, 2018 at 08:47:01AM +0100, Michel Pollet wrote:
> Add the RZ/N1 Family (Part #R9A06G0xx) ARCH config to the rest of
> the Renesas SoC collection.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[Simon Horman]

On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> Hi Michel
> 
> The subject of all your patches for arch/arm should start with:
> 
> ARM: dts:
> 
> A git log on that directory clearly shows that's the preferred one.
> 
> I would also say that you are missing a symbol definition in
> arch/arm/mach-shmobile/Kconfig
> (even if you got rid of any board file)
> 
> I would expect a symbol to select in menuconfig, with your
> dependencies listed there (ie, the serial interface driver)
> 
> Something like this (I left the 'xx' out from the part name on purpose)
> 
> diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
> index 280e731..9a519330 100644
> --- a/arch/arm/mach-shmobile/Kconfig
> +++ b/arch/arm/mach-shmobile/Kconfig
> @@ -114,4 +114,8 @@ config ARCH_SH73A0
>         bool "SH-Mobile AG5 (R8A73A00)"
>         select ARCH_RMOBILE
>         select RENESAS_INTC_IRQPIN
> +
> +config ARCH_R9A06G0
> +       bool "RZ/N1 (R9A06G0)"
> +       select SERIAL_8250_DW
>  endif
> 
> But please wait for others (preferibly Geert or Simon) to confim this.

I think that is covered by
"[PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig"

> On Thu, Mar 29, 2018 at 08:47:02AM +0100, Michel Pollet wrote:
> > This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> > bare bone support.
> >
> > This currently only handles generic parts (gic, architected timer)
> > and a UART.
> > For simplicity sake, this also relies on the bootloader to set the
> > pinctrl and clocks.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > ---
> >  arch/arm/boot/dts/r9a06g0xx.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 96 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
> >
> > diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi b/arch/arm/boot/dts/r9a06g0xx.dtsi
> > new file mode 100644
> > index 0000000..c6eeee3
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
> > @@ -0,0 +1,96 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Europe Limited
> > + *
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "renesas,rzn1";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a7";
> > +			reg = <0>;
> > +		};
> > +		cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a7";
> > +			reg = <1>;
> > +		};
> > +	};
> 
> I see you don't like empy lines, that's fine, it is not a strict
> requiremen afaik, but I find a few empty lines here and there more
> redable, expecially if the file is going to grow, as it will be.

Please place one empty line between each node.

> > +	clocks {
> > +		/*
> > +		 * this is fixed clock for now,
> > +		 * until the clock driver is merged
> > +		 */
> > +		clkuarts: clkuarts {
> 
> You can remove the node lable if it's the same as the node name afaik
> 
> > +			#clock-cells = <0>;
> > +			compatible = "fixed-clock";
> > +			clock-frequency = <47619047>;
> > +		};
> > +	};
> 
> Grouping clock nodes under a "clocks" one is now deprecated.
> 
> Please see, ie.
> "ARM: dts: r7s72100: stop grouping clocks under a "clocks" subnode"

Also, please sort sub-nodes of the root node alphabetically.

> Thanks
>    j
> 
> > +	arch-timer {
> > +		compatible = "arm,cortex-a7-timer",
> > +			     "arm,armv7-timer";
> > +		interrupt-parent = <&gic>;
> > +		arm,cpu-registers-not-fw-configured;
> > +		interrupts =
> > +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> > +				IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> > +				IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> > +				IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> > +				IRQ_TYPE_LEVEL_LOW)>;

I think its nicer not to line-wrap the individual interrupts.
I.e. please make the above like this:

		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

> > +	};
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		interrupt-parent = <&gic>;
> > +		ranges;
> > +
> > +		gic: gic@44101000 {

Please sort subnodes of the soc node using:
- Primary key of bus address
- Secondary key of IP block type (does not apply here)


> > +			compatible = "arm,cortex-a7-gic", "arm,gic-400";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			reg = <0x44101000 0x1000>, /* Distributer */
> > +			      <0x44102000 0x2000>, /* CPU interface */
> > +			      <0x44104000 0x2000>, /* Virt interface control */
> > +			      <0x44106000 0x2000>; /* Virt CPU interface */
> > +			interrupts =
> > +				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> > +					IRQ_TYPE_LEVEL_HIGH)>;
> > +		};
> > +		sysctrl: sysctrl@4000c000 {
> > +			compatible = "renesas,rzn1-sysctrl", "syscon",
> > +					"simple-mfd";
> > +			reg = <0x4000c000 0x1000>;
> > +
> > +			reboot {
> > +				compatible = "renesas,rzn1-reboot";
> > +			};
> > +		};
> > +		uart0: serial@40060000 {
> > +			compatible = "snps,dw-apb-uart";
> > +			reg = <0x40060000 0x400>;
> > +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > +			reg-shift = <2>;
> > +			reg-io-width = <4>;
> > +			clocks = <&clkuarts>;
> > +			clock-names = "baudclk";
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > --
> > 2.7.4
> >

Re: [PATCH v3 7/8] DT: arm: Add Renesas RZN1D-DB Board base file

[Simon Horman]

On Thu, Mar 29, 2018 at 08:47:03AM +0100, Michel Pollet wrote:
> This adds a base device tree file for the RZN1-DB board, with only the
> basic support allowing the system to boot to a prompt. Only one UART is
> used, with only a single CPU running.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> 
> diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> new file mode 100644
> index 0000000..a462b1a
> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the RZN1D-DB Board
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "r9a06g0xx.dtsi"
> +
> +/ {
> +	model = "RZN1D-DB Board";
> +	compatible = "renesas,rzn1d400-db", "renesas,r9a06g032", "renesas,rzn1";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +};
> +&uart0 {
> +	status = "okay";
> +};

Please add a blank line between nodes.
Please use "ARM: dts: " as the patch prefix.

Re: [PATCH v3 8/8] DT: arm: Add the RZN1D-DB Board to Renesas Makefile target

[Simon Horman]

On Thu, Mar 29, 2018 at 08:47:04AM +0100, Michel Pollet wrote:
> This adds the newly added board to the Renesas built target
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  arch/arm/boot/dts/Makefile | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8164c12..1849228 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -806,6 +806,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
>  	r8a7793-gose.dtb \
>  	r8a7794-alt.dtb \
>  	r8a7794-silk.dtb \
> +	r9a06g032-rzn1d400-db.dtb \
>  	sh73a0-kzm9g.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>  	rv1108-evb.dtb \

I think you can squash this patch into the one that adds the corresponding
dts file.

Re: [PATCH v3 1/8] DT: mfd: renesas,rzn1-sysctrl: document RZ/N1 sysctrl node

[Geert Uytterhoeven]

Hi Michel,

On Thu, Mar 29, 2018 at 9:46 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function
> system controller. This documents the node used to encapsulate
> it's sub drivers.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/renesas,rzn1-sysctrl.txt
> @@ -0,0 +1,19 @@
> +DT bindings for the Renesas RZ/N1 System Controller
> +
> +== System Controller Node ==
> +
> +The system controller node currently only hosts a single sub-node to handle
> +the rebooting of the CPU. Eventually it will host the clock driver, SMP
> +start handler, watchdog etc.
> +
> +See renesas,rzn1-reboot.txt for further details.
> +
> +Bindings:
> ++ Required:
> +       compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";

You should list the supported SoC-specific compatible values here.

> +
> +Example:
> +       sysctrl: sysctrl@4000c000 {
> +               compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";

Missing SoC-specific compatible value.

> +               reg = <0x4000c000 0x1000>;
> +       };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Geert Uytterhoeven]

Hi Michel,

On Thu, Mar 29, 2018 at 9:46 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> as part of the sysctrl MFD to handle rebooting the CA7 cores.
> This documents the driver bindings.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> @@ -0,0 +1,20 @@
> +DT bindings for the Renesas RZ/N1 Reboot Driver
> +
> +== Reboot Driver Node ==
> +
> +The reboot driver is always a subnode of the system controller node, see
> +renesas,rzn1-sysctrl.txt for details.
> +
> +Bindings:
> ++ Required:
> +       compatible = "renesas,rzn1-reboot";

You should list the supported SoC-specific compatible values here.

Quoting what I said on IRC:
1) DT bindings. These should list all compatible values possible/used.
2) DTS: These should list all applicable compatible values,
                from most-specific to least-specific (SoC-specific,
                family-specific (if exists), generic (if exists))
3 Driver: These should list only the least specific that is
                sufficient to get the job done. So usually we have the
                family-specific only, except if an SoC needs to be handled
                specially, or for historical reasons (DTB backeards
                compatibility)

> +
> +Example:
> +       sysctrl: sysctrl@4000c000 {
> +               compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";

Missing SoC-specific compatible value.

> +               reg = <0x4000c000 0x1000>;
> +
> +               reboot {
> +                       compatible = "renesas,rzn1-reboot";

Missing SoC-specific compatible value.

> +               };
> +       };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 3/8] DT: arm: renesas,rzn1: add the RZ/N1 SoC and RZN1D-DB board

[Geert Uytterhoeven]

Hi Michel,

On Thu, Mar 29, 2018 at 9:46 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> This documents the RZ/N1 bindings for both the RZ/N1 and the RZN1D-DB
> board.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/arm/shmobile.txt
> +++ b/Documentation/devicetree/bindings/arm/shmobile.txt
> @@ -47,7 +47,10 @@ SoCs:
>      compatible = "renesas,r8a77980"
>    - R-Car D3 (R8A77995)
>      compatible = "renesas,r8a77995"
> -
> +  - RZ/N1 Family (R9A06G032 & R9A06G033)
> +    compatible = "renesas,rzn1"
> +  - RZ/N1D (R9A06G032)
> +    compatible = "renesas,r9a06g032", "renesas,rzn1"

Is there any value in the family-specific "renesas,rzn1" compatible
value at the SoC
level? We don't have them for other Renesas SoC families.

We've been bitten before by values like "renesas,rspi-rz", not knowing
at that time
that Renesas was going to have multiple different RZ subfamilies.
Compare also e.g. R-Car W2H with other R-Car Gen2 SoCs...

Apart from that:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[Geert Uytterhoeven]

Hi Michel,

On Thu, Mar 29, 2018 at 9:47 AM, Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> bare bone support.
>
> This currently only handles generic parts (gic, architected timer)
> and a UART.
> For simplicity sake, this also relies on the bootloader to set the
> pinctrl and clocks.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g0xx.dtsi

As I said on IRC, I'm not so happy with this r9a06g0xx.dtsi file without
SoC-specific compatible values, as you have to override all of them in
r9a06g032.dtsi and r9a06g033.dtsi

Moreover, in this series you dropped r9a06g032.dtsi, so the devices no longer
have SoC-specific compatible values?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 5221 bytes --]

Hi Michel,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on renesas/devel]
[also build test ERROR on v4.16-rc7 next-20180329]
[cannot apply to robh/for-next power-supply/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Michel-Pollet/arm-Base-support-for-Renesas-RZN1D-DB-Board/20180330-103029
base:   https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git devel
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   drivers/power/reset/rzn1-reboot.c: In function 'rzn1_reboot_probe':
>> drivers/power/reset/rzn1-reboot.c:70:2: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
     if (!parent || !parent->of_node)
     ^~
   drivers/power/reset/rzn1-reboot.c:72:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
      return -ENODEV;
      ^~~~~~
   drivers/power/reset/rzn1-reboot.c:66:6: warning: unused variable 'err' [-Wunused-variable]
     int err;
         ^~~
   drivers/power/reset/rzn1-reboot.c: At top level:
>> drivers/power/reset/rzn1-reboot.c:74:2: warning: data definition has no type or storage class
     sysctrl = syscon_node_to_regmap(parent->of_node);
     ^~~~~~~
>> drivers/power/reset/rzn1-reboot.c:74:2: error: type defaults to 'int' in declaration of 'sysctrl' [-Werror=implicit-int]
>> drivers/power/reset/rzn1-reboot.c:74:2: error: conflicting types for 'sysctrl'
   drivers/power/reset/rzn1-reboot.c:37:23: note: previous declaration of 'sysctrl' was here
    static struct regmap *sysctrl;
                          ^~~~~~~
>> drivers/power/reset/rzn1-reboot.c:74:34: error: 'parent' undeclared here (not in a function); did you mean 'pte_t'?
     sysctrl = syscon_node_to_regmap(parent->of_node);
                                     ^~~~~~
                                     pte_t
>> drivers/power/reset/rzn1-reboot.c:75:2: error: expected identifier or '(' before 'if'
     if (IS_ERR(sysctrl)) {
     ^~
   drivers/power/reset/rzn1-reboot.c:79:2: warning: data definition has no type or storage class
     err = register_restart_handler(&rzn1_reboot_nb);
     ^~~
>> drivers/power/reset/rzn1-reboot.c:79:2: error: type defaults to 'int' in declaration of 'err' [-Werror=implicit-int]
>> drivers/power/reset/rzn1-reboot.c:79:8: error: initializer element is not constant
     err = register_restart_handler(&rzn1_reboot_nb);
           ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/power/reset/rzn1-reboot.c:80:2: error: expected identifier or '(' before 'if'
     if (err) {
     ^~
>> drivers/power/reset/rzn1-reboot.c:85:2: error: expected identifier or '(' before 'return'
     return err;
     ^~~~~~
>> drivers/power/reset/rzn1-reboot.c:86:1: error: expected identifier or '(' before '}' token
    }
    ^
   cc1: some warnings being treated as errors

vim +74 drivers/power/reset/rzn1-reboot.c

a673cd20 Michel Pollet 2018-03-29  63  
a673cd20 Michel Pollet 2018-03-29  64  static int rzn1_reboot_probe(struct platform_device *pdev)
a673cd20 Michel Pollet 2018-03-29  65  {
a673cd20 Michel Pollet 2018-03-29 @66  	int err;
a673cd20 Michel Pollet 2018-03-29  67  	struct device *parent;
a673cd20 Michel Pollet 2018-03-29  68  
a673cd20 Michel Pollet 2018-03-29  69  	parent = pdev->dev.parent;
a673cd20 Michel Pollet 2018-03-29 @70  	if (!parent || !parent->of_node)
a673cd20 Michel Pollet 2018-03-29  71  		dev_err(&pdev->dev, "couldn't find sysctrl node\n");
a673cd20 Michel Pollet 2018-03-29 @72  		return -ENODEV;
a673cd20 Michel Pollet 2018-03-29  73  	}
a673cd20 Michel Pollet 2018-03-29 @74  	sysctrl = syscon_node_to_regmap(parent->of_node);
a673cd20 Michel Pollet 2018-03-29 @75  	if (IS_ERR(sysctrl)) {
a673cd20 Michel Pollet 2018-03-29  76  		dev_err(&pdev->dev, "couldn't find find regmap\n");
a673cd20 Michel Pollet 2018-03-29  77  		return PTR_ERR(sysctrl);
a673cd20 Michel Pollet 2018-03-29  78  	}
a673cd20 Michel Pollet 2018-03-29 @79  	err = register_restart_handler(&rzn1_reboot_nb);
a673cd20 Michel Pollet 2018-03-29  80  	if (err) {
a673cd20 Michel Pollet 2018-03-29  81  		dev_err(&pdev->dev, "register restart handler failed(err=%d)\n",
a673cd20 Michel Pollet 2018-03-29  82  			err);
a673cd20 Michel Pollet 2018-03-29  83  	}
a673cd20 Michel Pollet 2018-03-29  84  
a673cd20 Michel Pollet 2018-03-29 @85  	return err;
a673cd20 Michel Pollet 2018-03-29 @86  }
a673cd20 Michel Pollet 2018-03-29  87  

:::::: The code at line 74 was first introduced by commit
:::::: a673cd202aba1924128e65ccd880b1eb5201c559 reset: Renesas RZ/N1 reboot driver

:::::: TO: Michel Pollet <michel.pollet@bp.renesas.com>
:::::: CC: 0day robot <fengguang.wu@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65137 bytes --]

Re: [PATCH v3 6/8] DT: arm: Add Renesas RZ/N1 SoC base device tree file

[jacopo mondi]

[-- Attachment #1: Type: text/plain, Size: 6337 bytes --]

Hi Simon, Michel,

On Fri, Mar 30, 2018 at 09:25:16AM +0200, Simon Horman wrote:
> On Thu, Mar 29, 2018 at 01:04:50PM +0200, jacopo mondi wrote:
> > Hi Michel
> >
> > The subject of all your patches for arch/arm should start with:
> >
> > ARM: dts:
> >
> > A git log on that directory clearly shows that's the preferred one.
> >
> > I would also say that you are missing a symbol definition in
> > arch/arm/mach-shmobile/Kconfig
> > (even if you got rid of any board file)
> >
> > I would expect a symbol to select in menuconfig, with your
> > dependencies listed there (ie, the serial interface driver)
> >
> > Something like this (I left the 'xx' out from the part name on purpose)
> >
> > diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
> > index 280e731..9a519330 100644
> > --- a/arch/arm/mach-shmobile/Kconfig
> > +++ b/arch/arm/mach-shmobile/Kconfig
> > @@ -114,4 +114,8 @@ config ARCH_SH73A0
> >         bool "SH-Mobile AG5 (R8A73A00)"
> >         select ARCH_RMOBILE
> >         select RENESAS_INTC_IRQPIN
> > +
> > +config ARCH_R9A06G0
> > +       bool "RZ/N1 (R9A06G0)"
> > +       select SERIAL_8250_DW
> >  endif
> >
> > But please wait for others (preferibly Geert or Simon) to confim this.
>
> I think that is covered by
> "[PATCH v3 5/8] arm: shmobile: Add the RZ/N1 arch to the shmobile Kconfig"
>

I somehow didn't apply that patch from the series when reviewing.

Sorry for the fuss.

Thanks
   j

> > On Thu, Mar 29, 2018 at 08:47:02AM +0100, Michel Pollet wrote:
> > > This adds the Renesas RZ/N1 Family (Part #R9A06G0xx) SoC
> > > bare bone support.
> > >
> > > This currently only handles generic parts (gic, architected timer)
> > > and a UART.
> > > For simplicity sake, this also relies on the bootloader to set the
> > > pinctrl and clocks.
> > >
> > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > > ---
> > >  arch/arm/boot/dts/r9a06g0xx.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 96 insertions(+)
> > >  create mode 100644 arch/arm/boot/dts/r9a06g0xx.dtsi
> > >
> > > diff --git a/arch/arm/boot/dts/r9a06g0xx.dtsi b/arch/arm/boot/dts/r9a06g0xx.dtsi
> > > new file mode 100644
> > > index 0000000..c6eeee3
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/r9a06g0xx.dtsi
> > > @@ -0,0 +1,96 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Base Device Tree Source for the Renesas RZ/N1 SoC Family of devices
> > > + *
> > > + * Copyright (C) 2018 Renesas Electronics Europe Limited
> > > + *
> > > + */
> > > +
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +/ {
> > > +	compatible = "renesas,rzn1";
> > > +	#address-cells = <1>;
> > > +	#size-cells = <1>;
> > > +
> > > +	cpus {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		cpu@0 {
> > > +			device_type = "cpu";
> > > +			compatible = "arm,cortex-a7";
> > > +			reg = <0>;
> > > +		};
> > > +		cpu@1 {
> > > +			device_type = "cpu";
> > > +			compatible = "arm,cortex-a7";
> > > +			reg = <1>;
> > > +		};
> > > +	};
> >
> > I see you don't like empy lines, that's fine, it is not a strict
> > requiremen afaik, but I find a few empty lines here and there more
> > redable, expecially if the file is going to grow, as it will be.
>
> Please place one empty line between each node.
>
> > > +	clocks {
> > > +		/*
> > > +		 * this is fixed clock for now,
> > > +		 * until the clock driver is merged
> > > +		 */
> > > +		clkuarts: clkuarts {
> >
> > You can remove the node lable if it's the same as the node name afaik
> >
> > > +			#clock-cells = <0>;
> > > +			compatible = "fixed-clock";
> > > +			clock-frequency = <47619047>;
> > > +		};
> > > +	};
> >
> > Grouping clock nodes under a "clocks" one is now deprecated.
> >
> > Please see, ie.
> > "ARM: dts: r7s72100: stop grouping clocks under a "clocks" subnode"
>
> Also, please sort sub-nodes of the root node alphabetically.
>
> > Thanks
> >    j
> >
> > > +	arch-timer {
> > > +		compatible = "arm,cortex-a7-timer",
> > > +			     "arm,armv7-timer";
> > > +		interrupt-parent = <&gic>;
> > > +		arm,cpu-registers-not-fw-configured;
> > > +		interrupts =
> > > +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> > > +				IRQ_TYPE_LEVEL_LOW)>,
> > > +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> > > +				IRQ_TYPE_LEVEL_LOW)>,
> > > +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> > > +				IRQ_TYPE_LEVEL_LOW)>,
> > > +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> > > +				IRQ_TYPE_LEVEL_LOW)>;
>
> I think its nicer not to line-wrap the individual interrupts.
> I.e. please make the above like this:
>
> 		interrupts =
> 			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> 			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> 			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> 			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>
> > > +	};
> > > +	soc {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		interrupt-parent = <&gic>;
> > > +		ranges;
> > > +
> > > +		gic: gic@44101000 {
>
> Please sort subnodes of the soc node using:
> - Primary key of bus address
> - Secondary key of IP block type (does not apply here)
>
>
> > > +			compatible = "arm,cortex-a7-gic", "arm,gic-400";
> > > +			interrupt-controller;
> > > +			#interrupt-cells = <3>;
> > > +			reg = <0x44101000 0x1000>, /* Distributer */
> > > +			      <0x44102000 0x2000>, /* CPU interface */
> > > +			      <0x44104000 0x2000>, /* Virt interface control */
> > > +			      <0x44106000 0x2000>; /* Virt CPU interface */
> > > +			interrupts =
> > > +				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> > > +					IRQ_TYPE_LEVEL_HIGH)>;
> > > +		};
> > > +		sysctrl: sysctrl@4000c000 {
> > > +			compatible = "renesas,rzn1-sysctrl", "syscon",
> > > +					"simple-mfd";
> > > +			reg = <0x4000c000 0x1000>;
> > > +
> > > +			reboot {
> > > +				compatible = "renesas,rzn1-reboot";
> > > +			};
> > > +		};
> > > +		uart0: serial@40060000 {
> > > +			compatible = "snps,dw-apb-uart";
> > > +			reg = <0x40060000 0x400>;
> > > +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > > +			reg-shift = <2>;
> > > +			reg-io-width = <4>;
> > > +			clocks = <&clkuarts>;
> > > +			clock-names = "baudclk";
> > > +			status = "disabled";
> > > +		};
> > > +	};
> > > +};
> > > --
> > > 2.7.4
> > >
>
>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Rob Herring]

On Thu, Mar 29, 2018 at 08:46:58AM +0100, Michel Pollet wrote:
> The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
> as part of the sysctrl MFD to handle rebooting the CA7 cores.
> This documents the driver bindings.
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> ---
>  .../bindings/power/renesas,rzn1-reboot.txt           | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> new file mode 100644
> index 0000000..f592769
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> @@ -0,0 +1,20 @@
> +DT bindings for the Renesas RZ/N1 Reboot Driver
> +
> +== Reboot Driver Node ==
> +
> +The reboot driver is always a subnode of the system controller node, see
> +renesas,rzn1-sysctrl.txt for details.
> +
> +Bindings:
> ++ Required:
> +	compatible = "renesas,rzn1-reboot";
> +
> +Example:
> +	sysctrl: sysctrl@4000c000 {
> +		compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";

Are there other functions for this block? If so, please define a 
complete binding for the block.

> +		reg = <0x4000c000 0x1000>;
> +
> +		reboot {
> +			compatible = "renesas,rzn1-reboot";

Why is this node needed? The driver for "renesas,rzn1-sysctrl" should 
be able to register as a reboot handler/driver/provider.

Rob

RE: [PATCH v3 2/8] DT: reset: renesas,rzn1-reboot: document RZ/N1 reboot driver

[Michel Pollet]

Hi Rob,

On 09 April 2018 21:10,  Rob Herring wrote:
> On Thu, Mar 29, 2018 at 08:46:58AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver as part
> > of the sysctrl MFD to handle rebooting the CA7 cores.
> > This documents the driver bindings.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > ---
> >  .../bindings/power/renesas,rzn1-reboot.txt           | 20
> ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> > b/Documentation/devicetree/bindings/power/renesas,rzn1-reboot.txt
> > new file mode 100644
> > index 0000000..f592769
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/power/renesas,rzn1-
> reboot.txt
> > @@ -0,0 +1,20 @@
> > +DT bindings for the Renesas RZ/N1 Reboot Driver
> > +
> > +== Reboot Driver Node ==
> > +
> > +The reboot driver is always a subnode of the system controller node,
> > +see renesas,rzn1-sysctrl.txt for details.
> > +
> > +Bindings:
> > ++ Required:
> > +compatible = "renesas,rzn1-reboot";
> > +
> > +Example:
> > +sysctrl: sysctrl@4000c000 {
> > +compatible = "renesas,rzn1-sysctrl", "syscon", "simple-mfd";
>
> Are there other functions for this block? If so, please define a complete
> binding for the block.

There are indeed multiple functions for this particular IP block. It's pretty much a
kitchen sink of clocks, pinmux, reboot, watchdog, SMP and probably a couple
more I forgot about!

We've discussed this MFD structure with Geert, we picked that because if I
were to add all these callbacks/drivers to a 'sysctrl' driver, it'd end up looking
like ... a mach-xx.c file in the end!
So the current version is just a placeholder for a single driver for now, but it
won't last, there's already a SMP core enable driver lined up next...

>
> > +reg = <0x4000c000 0x1000>;
> > +
> > +reboot {
> > +compatible = "renesas,rzn1-reboot";
>
> Why is this node needed? The driver for "renesas,rzn1-sysctrl" should be
> able to register as a reboot handler/driver/provider.

Please see above...

>
> Rob

Thanks for your input!
Michel




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.