* [PATCH 0/2] pinctrl: sh-pfc: r8a7799[05]: Fix MOD_SEL bit numbering @ 2018-12-12 10:19 Yoshihiro Shimoda 2018-12-12 10:19 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: " Yoshihiro Shimoda 2018-12-12 10:19 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77995: " Yoshihiro Shimoda 0 siblings, 2 replies; 7+ messages in thread From: Yoshihiro Shimoda @ 2018-12-12 10:19 UTC (permalink / raw) To: geert+renesas, linus.walleij Cc: linux-renesas-soc, linux-gpio, Yoshihiro Shimoda This patch set fixes the issue that some MOD_SEL setting is incorrect on r8a7799[05] SoCs. Takeshi Kihara (2): pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 28 ++++++++++++++-------------- drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 8 ++++---- 2 files changed, 18 insertions(+), 18 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering 2018-12-12 10:19 [PATCH 0/2] pinctrl: sh-pfc: r8a7799[05]: Fix MOD_SEL bit numbering Yoshihiro Shimoda @ 2018-12-12 10:19 ` Yoshihiro Shimoda 2018-12-20 14:05 ` Geert Uytterhoeven 2018-12-12 10:19 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77995: " Yoshihiro Shimoda 1 sibling, 1 reply; 7+ messages in thread From: Yoshihiro Shimoda @ 2018-12-12 10:19 UTC (permalink / raw) To: geert+renesas, linus.walleij Cc: linux-renesas-soc, linux-gpio, Takeshi Kihara, Yoshihiro Shimoda From: Takeshi Kihara <takeshi.kihara.df@renesas.com> MOD_SEL register bit numbering was different from R-Car E3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] E3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") [shimoda: split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 8c06d72..8c75d31 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -392,28 +392,28 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0) +#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_2) FM(SEL_ADGB_1) F_(0, 0) #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) -#define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0) +#define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_2) FM(SEL_FM_1) F_(0, 0) #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) -#define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) FM(SEL_I2C1_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_2) FM(SEL_I2C1_1) FM(SEL_I2C1_3) +#define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_4) FM(SEL_I2C2_2) F_(0, 0) FM(SEL_I2C2_1) F_(0, 0) FM(SEL_I2C2_3) F_(0, 0) #define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) -#define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0) -#define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0) +#define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_2) FM(SEL_PWM2_1) F_(0, 0) +#define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_2) FM(SEL_PWM3_1) F_(0, 0) #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) -#define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0) +#define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_2) FM(SEL_REMOCON_1) F_(0, 0) #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) -#define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0) +#define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_2) FM(SEL_SPEED_PULSE_IF_1) F_(0, 0) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) @@ -422,18 +422,18 @@ #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) -#define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_4) FM(SEL_HSCIF3_2) F_(0, 0) FM(SEL_HSCIF3_1) F_(0, 0) FM(SEL_HSCIF3_3) F_(0, 0) +#define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_4) FM(SEL_HSCIF4_2) F_(0, 0) FM(SEL_HSCIF4_1) F_(0, 0) FM(SEL_HSCIF4_3) F_(0, 0) #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) -#define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0) -#define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) -#define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0) +#define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_2) FM(SEL_SCIF3_1) F_(0, 0) +#define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_2) FM(SEL_SCIF4_1) F_(0, 0) +#define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_2) FM(SEL_SCIF5_1) F_(0, 0) #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) -#define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0) +#define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_2) FM(SEL_ADGC_1) F_(0, 0) #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define PINMUX_MOD_SELS \ -- 1.9.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering 2018-12-12 10:19 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: " Yoshihiro Shimoda @ 2018-12-20 14:05 ` Geert Uytterhoeven 0 siblings, 0 replies; 7+ messages in thread From: Geert Uytterhoeven @ 2018-12-20 14:05 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: Geert Uytterhoeven, Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM, Takeshi Kihara Hi Shimoda-san, On Wed, Dec 12, 2018 at 11:22 AM Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > MOD_SEL register bit numbering was different from R-Car E3 SoC and > R-Car H3/M3-[WN] SoCs. > > MOD_SEL 1-bit H3/M3-[WN] E3 > =============== ========== ===== > Set Value = H'0 b'0 b'0 > Set Value = H'1 b'1 b'1 > > MOD_SEL 2-bits H3/M3-[WN] E3 > =============== ========== ===== > Set Value = H'0 b'00 b'00 > Set Value = H'1 b'01 b'10 > Set Value = H'2 b'10 b'01 > Set Value = H'3 b'11 b'11 > > MOD_SEL 3-bits H3/M3-[WN] E3 > =============== ========== ===== > Set Value = H'0 b'000 b'000 > Set Value = H'1 b'001 b'100 > Set Value = H'2 b'010 b'010 > Set Value = H'3 b'011 b'110 > Set Value = H'4 b'100 b'001 > Set Value = H'5 b'101 b'101 > Set Value = H'6 b'110 b'011 > Set Value = H'7 b'111 b'111 > > This patch replaces the #define name and value of MOD_SEL. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Fixes: 6d4036a1e3b3 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") > [shimoda: split a patch per SoC and revise the commit log] > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Thanks, this fixes HSCIF4(B) RX. > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c > @@ -392,28 +392,28 @@ > FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 > > /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ > -#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0) > +#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_2) FM(SEL_ADGB_1) F_(0, 0) As this is not a plain reversal, but reordering based on the reverse of the binary value, I think this would be easier to read if you would use a macro to do the reordering. I sent a patch showing what I had in mind. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 2018-12-12 10:19 [PATCH 0/2] pinctrl: sh-pfc: r8a7799[05]: Fix MOD_SEL bit numbering Yoshihiro Shimoda 2018-12-12 10:19 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: " Yoshihiro Shimoda @ 2018-12-12 10:19 ` Yoshihiro Shimoda 2018-12-13 13:52 ` Laurent Pinchart 1 sibling, 1 reply; 7+ messages in thread From: Yoshihiro Shimoda @ 2018-12-12 10:19 UTC (permalink / raw) To: geert+renesas, linus.walleij Cc: linux-renesas-soc, linux-gpio, Takeshi Kihara, Yoshihiro Shimoda From: Takeshi Kihara <takeshi.kihara.df@renesas.com> MOD_SEL register bit numbering was different from R-Car D3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") [shimoda: split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> --- drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index e457539..e0db6f3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -388,10 +388,10 @@ #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) -#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3) -#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3) -#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3) -#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3) +#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_2) FM(SEL_PWM0_1) FM(SEL_PWM0_3) +#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_2) FM(SEL_PWM1_1) FM(SEL_PWM1_3) +#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_2) FM(SEL_PWM2_1) FM(SEL_PWM2_3) +#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_2) FM(SEL_PWM3_1) FM(SEL_PWM3_3) #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) -- 1.9.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 2018-12-12 10:19 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77995: " Yoshihiro Shimoda @ 2018-12-13 13:52 ` Laurent Pinchart 2018-12-14 10:41 ` Yoshihiro Shimoda 0 siblings, 1 reply; 7+ messages in thread From: Laurent Pinchart @ 2018-12-13 13:52 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: geert+renesas, linus.walleij, linux-renesas-soc, linux-gpio, Takeshi Kihara Hello Shimoda-san, Thank you for the patch. On Wednesday, 12 December 2018 12:19:35 EET Yoshihiro Shimoda wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > MOD_SEL register bit numbering was different from R-Car D3 SoC and > R-Car H3/M3-[WN] SoCs. > > MOD_SEL 1-bit H3/M3-[WN] D3 > =============== ========== ===== > Set Value = H'0 b'0 b'0 > Set Value = H'1 b'1 b'1 > > MOD_SEL 2-bits H3/M3-[WN] D3 > =============== ========== ===== > Set Value = H'0 b'00 b'00 > Set Value = H'1 b'01 b'10 > Set Value = H'2 b'10 b'01 > Set Value = H'3 b'11 b'11 > > MOD_SEL 3-bits H3/M3-[WN] D3 > =============== ========== ===== > Set Value = H'0 b'000 b'000 > Set Value = H'1 b'001 b'100 > Set Value = H'2 b'010 b'010 > Set Value = H'3 b'011 b'110 > Set Value = H'4 b'100 b'001 > Set Value = H'5 b'101 b'101 > Set Value = H'6 b'110 b'011 > Set Value = H'7 b'111 b'111 > > This patch replaces the #define name and value of MOD_SEL. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") > [shimoda: split a patch per SoC and revise the commit log] > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Per Geert's request I've tested this patch on the Draak board with pwm- backlight, and it doesn't seem to make any difference. > --- > drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c > b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index e457539..e0db6f3 100644 > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c > @@ -388,10 +388,10 @@ > #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) > #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) > #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) > -#define > MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0 > _3) -#define > MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1 > _3) -#define > MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2 > _3) -#define > MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3 > _3) +#define > MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_2) FM(SEL_PWM0_1) FM(SEL_PWM0 > _3) +#define > MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_2) FM(SEL_PWM1_1) FM(SEL_PWM1 > _3) +#define > MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_2) FM(SEL_PWM2_1) FM(SEL_PWM2 > _3) +#define > MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_2) FM(SEL_PWM3_1) FM(SEL_PWM3 > _3) #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) > #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) > #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 2/2] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 2018-12-13 13:52 ` Laurent Pinchart @ 2018-12-14 10:41 ` Yoshihiro Shimoda 2018-12-14 12:51 ` Laurent Pinchart 0 siblings, 1 reply; 7+ messages in thread From: Yoshihiro Shimoda @ 2018-12-14 10:41 UTC (permalink / raw) To: Laurent Pinchart Cc: geert+renesas, linus.walleij, linux-renesas-soc, linux-gpio, TAKESHI KIHARA Hi Laurent-san, > From: Laurent Pinchart, Sent: Thursday, December 13, 2018 10:53 PM > > Hello Shimoda-san, > > Thank you for the patch. > > On Wednesday, 12 December 2018 12:19:35 EET Yoshihiro Shimoda wrote: > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > > > MOD_SEL register bit numbering was different from R-Car D3 SoC and > > R-Car H3/M3-[WN] SoCs. > > > > MOD_SEL 1-bit H3/M3-[WN] D3 > > =============== ========== ===== > > Set Value = H'0 b'0 b'0 > > Set Value = H'1 b'1 b'1 > > > > MOD_SEL 2-bits H3/M3-[WN] D3 > > =============== ========== ===== > > Set Value = H'0 b'00 b'00 > > Set Value = H'1 b'01 b'10 > > Set Value = H'2 b'10 b'01 > > Set Value = H'3 b'11 b'11 > > > > MOD_SEL 3-bits H3/M3-[WN] D3 > > =============== ========== ===== > > Set Value = H'0 b'000 b'000 > > Set Value = H'1 b'001 b'100 > > Set Value = H'2 b'010 b'010 > > Set Value = H'3 b'011 b'110 > > Set Value = H'4 b'100 b'001 > > Set Value = H'5 b'101 b'101 > > Set Value = H'6 b'110 b'011 > > Set Value = H'7 b'111 b'111 > > > > This patch replaces the #define name and value of MOD_SEL. > > > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") > > [shimoda: split a patch per SoC and revise the commit log] > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > Per Geert's request I've tested this patch on the Draak board with pwm- > backlight, and it doesn't seem to make any difference. Thank you for testing this patch! The result seems strange to me. So, I'll investigate it in next week. Best regards, Yoshihiro Shimoda ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering 2018-12-14 10:41 ` Yoshihiro Shimoda @ 2018-12-14 12:51 ` Laurent Pinchart 0 siblings, 0 replies; 7+ messages in thread From: Laurent Pinchart @ 2018-12-14 12:51 UTC (permalink / raw) To: Yoshihiro Shimoda Cc: geert+renesas, linus.walleij, linux-renesas-soc, linux-gpio, TAKESHI KIHARA Hello Shimoda-san, On Friday, 14 December 2018 12:41:32 EET Yoshihiro Shimoda wrote: > From: Laurent Pinchart, Sent: Thursday, December 13, 2018 10:53 PM > > On Wednesday, 12 December 2018 12:19:35 EET Yoshihiro Shimoda wrote: > > > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > > > > > MOD_SEL register bit numbering was different from R-Car D3 SoC and > > > R-Car H3/M3-[WN] SoCs. > > > > > > MOD_SEL 1-bit H3/M3-[WN] D3 > > > =============== ========== ===== > > > Set Value = H'0 b'0 b'0 > > > Set Value = H'1 b'1 b'1 > > > > > > MOD_SEL 2-bits H3/M3-[WN] D3 > > > =============== ========== ===== > > > Set Value = H'0 b'00 b'00 > > > Set Value = H'1 b'01 b'10 > > > Set Value = H'2 b'10 b'01 > > > Set Value = H'3 b'11 b'11 > > > > > > MOD_SEL 3-bits H3/M3-[WN] D3 > > > =============== ========== ===== > > > Set Value = H'0 b'000 b'000 > > > Set Value = H'1 b'001 b'100 > > > Set Value = H'2 b'010 b'010 > > > Set Value = H'3 b'011 b'110 > > > Set Value = H'4 b'100 b'001 > > > Set Value = H'5 b'101 b'101 > > > Set Value = H'6 b'110 b'011 > > > Set Value = H'7 b'111 b'111 > > > > > > This patch replaces the #define name and value of MOD_SEL. > > > > > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > > Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") > > > [shimoda: split a patch per SoC and revise the commit log] > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > > > > Per Geert's request I've tested this patch on the Draak board with pwm- > > backlight, and it doesn't seem to make any difference. > > Thank you for testing this patch! > The result seems strange to me. So, I'll investigate it in next week. My guess is that MOD_SEL only affects input signals, not output signals. -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-12-20 14:06 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-12-12 10:19 [PATCH 0/2] pinctrl: sh-pfc: r8a7799[05]: Fix MOD_SEL bit numbering Yoshihiro Shimoda 2018-12-12 10:19 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: " Yoshihiro Shimoda 2018-12-20 14:05 ` Geert Uytterhoeven 2018-12-12 10:19 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77995: " Yoshihiro Shimoda 2018-12-13 13:52 ` Laurent Pinchart 2018-12-14 10:41 ` Yoshihiro Shimoda 2018-12-14 12:51 ` Laurent Pinchart
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