[PATCH 00/11] Add basic EK874 support

[PATCH 00/11] Add basic EK874 support

[Fabrizio Castro]

Dear All,

The EK874 is an evaluation kit for the RZ/G2E SoC (a.k.a. r8a774c0)
from Silicon Linux Corporation. It is made of two boards: cat874
(the main board) and cat875 (the sub board).

This series adds the device trees to describe the HW configuration
of the EK874, with some basic support.

This applies onto next-20190116

Thanks,
Fab

Biju Das (6):
  dt-bindings: Add vendor prefix for Silicon Linux.
  arm64: dts: renesas: Add Si-Linux CAT874 board support
  arm64: dts: renesas: Add Si-Linux EK874 board support
  arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2
  arm64: dts: renesas: r8a774c0-cat874: Add uSD support
  arm64: dts: renesas: cat875: Add ethernet support

Fabrizio Castro (5):
  dt-bindings: arm: renesas: Add si-linux cat87[45] boards
  clk: renesas: r8a774c0: Add missing CANFD clock
  dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks
  arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes
  dt-bindings: can: rcar_canfd: document r8a774c0 support

 Documentation/devicetree/bindings/arm/renesas.yaml |  8 ++
 .../devicetree/bindings/net/can/rcar_can.txt       | 12 +--
 .../devicetree/bindings/net/can/rcar_canfd.txt     | 16 ++--
 .../devicetree/bindings/vendor-prefixes.txt        |  1 +
 arch/arm64/boot/dts/renesas/Makefile               |  1 +
 arch/arm64/boot/dts/renesas/cat875.dtsi            | 40 +++++++++
 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts    | 97 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts     | 14 ++++
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi          | 12 ++-
 drivers/clk/renesas/r8a774c0-cpg-mssr.c            |  4 +
 include/dt-bindings/clock/r8a774c0-cpg-mssr.h      | 17 ++--
 11 files changed, 194 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/cat875.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts

-- 
2.7.4

[PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

Add Silicon Linux to the list of devicetree vendor prefixes.

Website: http://www.si-linux.co.jp

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 4b1a2a8..02a7037 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -344,6 +344,7 @@ sgx	SGX Sensortech
 sharp	Sharp Corporation
 shimafuji	Shimafuji Electric, Inc.
 si-en	Si-En Technology Ltd.
+si-linux	Silicon Linux Corporation
 sifive	SiFive, Inc.
 sigma	Sigma Designs, Inc.
 sii	Seiko Instruments, Inc.
-- 
2.7.4

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:44PM +0000, Fabrizio Castro wrote:
> From: Biju Das <biju.das@bp.renesas.com>
> 
> Add Silicon Linux to the list of devicetree vendor prefixes.
> 
> Website: http://www.si-linux.co.jp
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 4b1a2a8..02a7037 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -344,6 +344,7 @@ sgx	SGX Sensortech
>  sharp	Sharp Corporation
>  shimafuji	Shimafuji Electric, Inc.
>  si-en	Si-En Technology Ltd.
> +si-linux	Silicon Linux Corporation
>  sifive	SiFive, Inc.
>  sigma	Sigma Designs, Inc.
>  sii	Seiko Instruments, Inc.
> -- 
> 2.7.4
> 

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Andreas Färber]

Hi Fabrizio,

Am 16.01.19 um 19:37 schrieb Fabrizio Castro:
> From: Biju Das <biju.das@bp.renesas.com>
> 
> Add Silicon Linux to the list of devicetree vendor prefixes.
> 
> Website: http://www.si-linux.co.jp
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 4b1a2a8..02a7037 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -344,6 +344,7 @@ sgx	SGX Sensortech
>  sharp	Sharp Corporation
>  shimafuji	Shimafuji Electric, Inc.
>  si-en	Si-En Technology Ltd.
> +si-linux	Silicon Linux Corporation

With the website being Japanese only, I haven't been able to confirm the
spelling of the company name. Looks sensible though.

Due to "en" coming before "five" I've double-checked that elsewhere we
do order dashes before letters, so placement in file and tab-indentation
is fine, too.

>  sifive	SiFive, Inc.
>  sigma	Sigma Designs, Inc.
>  sii	Seiko Instruments, Inc.

Personally I would drop the full stop at the end of the subject, but anyway:

Reviewed-by: Andreas Färber <afaerber@suse.de>

Thanks,
Andreas

P.S. Please double-check how this excessive CC list came to life!

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Simon Horman]

On Thu, Jan 17, 2019 at 12:17:56PM +0100, Andreas Färber wrote:
> Hi Fabrizio,
> 
> Am 16.01.19 um 19:37 schrieb Fabrizio Castro:
> > From: Biju Das <biju.das@bp.renesas.com>
> > 
> > Add Silicon Linux to the list of devicetree vendor prefixes.
> > 
> > Website: http://www.si-linux.co.jp
> > 
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > ---
> >  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > index 4b1a2a8..02a7037 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > @@ -344,6 +344,7 @@ sgx	SGX Sensortech
> >  sharp	Sharp Corporation
> >  shimafuji	Shimafuji Electric, Inc.
> >  si-en	Si-En Technology Ltd.
> > +si-linux	Silicon Linux Corporation
> 
> With the website being Japanese only, I haven't been able to confirm the
> spelling of the company name. Looks sensible though.

According to the company web site
(http://si-linux.co.jp/index.php?%E4%BC%9A%E7%A4%BE%E6%A1%88%E5%86%85)
the company name is.

Japanese: シリコンリナックス株式会社
English:  Silicon Linux Corporation

And in my opinion these are equivalent (although other translations of
the corporation bit are possible).

> Due to "en" coming before "five" I've double-checked that elsewhere we
> do order dashes before letters, so placement in file and tab-indentation
> is fine, too.
> 
> >  sifive	SiFive, Inc.
> >  sigma	Sigma Designs, Inc.
> >  sii	Seiko Instruments, Inc.
> 
> Personally I would drop the full stop at the end of the subject, but anyway:
> 
> Reviewed-by: Andreas Färber <afaerber@suse.de>
> 
> Thanks,
> Andreas
> 
> P.S. Please double-check how this excessive CC list came to life!
> 
> -- 
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer, Jane Smithard, Graham Norton
> HRB 21284 (AG Nürnberg)
> 

RE: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Chris Paterson]

Hello Andreas, Simon,

Thank you for your reviews.

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 January 2019 12:19
> 
> On Thu, Jan 17, 2019 at 12:17:56PM +0100, Andreas Färber wrote:
> > Hi Fabrizio,
> >
> > Am 16.01.19 um 19:37 schrieb Fabrizio Castro:
> > > From: Biju Das <biju.das@bp.renesas.com>
> > >
> > > Add Silicon Linux to the list of devicetree vendor prefixes.
> > >
> > > Website: http://www.si-linux.co.jp
> > >
> > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > > ---
> > >  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > index 4b1a2a8..02a7037 100644
> > > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > @@ -344,6 +344,7 @@ sgx	SGX Sensortech
> > >  sharp	Sharp Corporation
> > >  shimafuji	Shimafuji Electric, Inc.
> > >  si-en	Si-En Technology Ltd.
> > > +si-linux	Silicon Linux Corporation
> >
> > With the website being Japanese only, I haven't been able to confirm the
> > spelling of the company name. Looks sensible though.
> 
> According to the company web site
> (http://si-
> linux.co.jp/index.php?%E4%BC%9A%E7%A4%BE%E6%A1%88%E5%86%85)
> the company name is.
> 
> Japanese: シリコンリナックス株式会社
> English:  Silicon Linux Corporation

I can also confirm that this is what we've been told by Si-Linux themselves 😊

Kind regards, Chris

> 
> And in my opinion these are equivalent (although other translations of
> the corporation bit are possible).
> 
> > Due to "en" coming before "five" I've double-checked that elsewhere we
> > do order dashes before letters, so placement in file and tab-indentation
> > is fine, too.
> >
> > >  sifive	SiFive, Inc.
> > >  sigma	Sigma Designs, Inc.
> > >  sii	Seiko Instruments, Inc.
> >
> > Personally I would drop the full stop at the end of the subject, but anyway:
> >
> > Reviewed-by: Andreas Färber <afaerber@suse.de>
> >
> > Thanks,
> > Andreas
> >
> > P.S. Please double-check how this excessive CC list came to life!
> >
> > --
> > SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> > GF: Felix Imendörffer, Jane Smithard, Graham Norton
> > HRB 21284 (AG Nürnberg)
> >

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Rob Herring]

On Wed, 16 Jan 2019 18:37:44 +0000, Fabrizio Castro wrote:
> From: Biju Das <biju.das@bp.renesas.com>
> 
> Add Silicon Linux to the list of devicetree vendor prefixes.
> 
> Website: http://www.si-linux.co.jp
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Fabrizio Castro]

Dear All,

Who is the best person for taking this patch?

Thanks,
Fab

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Sent: 16 January 2019 18:38
> Subject: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.
>
> From: Biju Das <biju.das@bp.renesas.com>
>
> Add Silicon Linux to the list of devicetree vendor prefixes.
>
> Website: http://www.si-linux.co.jp
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 4b1a2a8..02a7037 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -344,6 +344,7 @@ sgxSGX Sensortech
>  sharpSharp Corporation
>  shimafujiShimafuji Electric, Inc.
>  si-enSi-En Technology Ltd.
> +si-linuxSilicon Linux Corporation
>  sifiveSiFive, Inc.
>  sigmaSigma Designs, Inc.
>  siiSeiko Instruments, Inc.
> --
> 2.7.4



Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Lukasz Majewski]

[-- Attachment #1: Type: text/plain, Size: 2157 bytes --]

Hi Fabrizio,

The best approach is to run:

git format patch -1 <your patch sha>

And then 

scripts/get_maintainer.pl 0001-xxxxxxx

You shall see the the list of people to send the patch.

> Dear All,
> 
> Who is the best person for taking this patch?
> 
> Thanks,
> Fab
> 
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Sent: 16 January 2019 18:38
> > Subject: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon
> > Linux.
> >
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > Add Silicon Linux to the list of devicetree vendor prefixes.
> >
> > Website: http://www.si-linux.co.jp
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > ---
> >  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > b/Documentation/devicetree/bindings/vendor-prefixes.txt index
> > 4b1a2a8..02a7037 100644 ---
> > a/Documentation/devicetree/bindings/vendor-prefixes.txt +++
> > b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -344,6
> > +344,7 @@ sgxSGX Sensortech sharpSharp Corporation
> >  shimafujiShimafuji Electric, Inc.
> >  si-enSi-En Technology Ltd.
> > +si-linuxSilicon Linux Corporation
> >  sifiveSiFive, Inc.
> >  sigmaSigma Designs, Inc.
> >  siiSeiko Instruments, Inc.
> > --
> > 2.7.4  
> 
> 
> 
> Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael
> Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf,
> Arcadiastrasse 10, 40472 Duesseldorf,
> Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708
> USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE
> reg. no.: DE 14978647




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Andreas Färber]

Hi Lukasz and Fabrizio,

Am 15.02.19 um 07:52 schrieb Lukasz Majewski:
> The best approach is to run:
> 
> git format patch -1 <your patch sha>
> 
> And then 
> 
> scripts/get_maintainer.pl 0001-xxxxxxx
> 
> You shall see the the list of people to send the patch.

No, that does not answer his question. And please don't top-post.

>> Who is the best person for taking this patch?

The answer is: whomever is taking dt-bindings patches in the following
10 patches that make use of this prefix, once you have a Reviewed-by
from Rob. So, most likely the Renesas kernel maintainer(s), i.e. Simon,
which differs from get_maintainers.pl of vendor-prefixes.txt.

Regards,
Andreas

>>> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>> Sent: 16 January 2019 18:38
>>> Subject: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon
>>> Linux.
>>>
>>> From: Biju Das <biju.das@bp.renesas.com>
>>>
>>> Add Silicon Linux to the list of devicetree vendor prefixes.
>>>
>>> Website: http://www.si-linux.co.jp
>>>
>>> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>>> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
>>> ---
>>>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
>>> b/Documentation/devicetree/bindings/vendor-prefixes.txt index
>>> 4b1a2a8..02a7037 100644 ---
>>> a/Documentation/devicetree/bindings/vendor-prefixes.txt +++
>>> b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -344,6
>>> +344,7 @@ sgxSGX Sensortech sharpSharp Corporation
>>>  shimafujiShimafuji Electric, Inc.
>>>  si-enSi-En Technology Ltd.
>>> +si-linuxSilicon Linux Corporation
>>>  sifiveSiFive, Inc.
>>>  sigmaSigma Designs, Inc.
>>>  siiSeiko Instruments, Inc.
>>> --
>>> 2.7.4  
>>
>>
>>
>> Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael
>> Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf,
>> Arcadiastrasse 10, 40472 Duesseldorf,
>> Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708
>> USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE
>> reg. no.: DE 14978647
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
> 


-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

RE: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Fabrizio Castro]

Thank you Andreas.

> From: Andreas Färber <afaerber@suse.de>
> Sent: 15 February 2019 09:10
> Subject: Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.
> 
> Hi Lukasz and Fabrizio,
> 
> Am 15.02.19 um 07:52 schrieb Lukasz Majewski:
> > The best approach is to run:
> >
> > git format patch -1 <your patch sha>
> >
> > And then
> >
> > scripts/get_maintainer.pl 0001-xxxxxxx
> >
> > You shall see the the list of people to send the patch.
> 
> No, that does not answer his question. And please don't top-post.
> 
> >> Who is the best person for taking this patch?
> 
> The answer is: whomever is taking dt-bindings patches in the following
> 10 patches that make use of this prefix, once you have a Reviewed-by
> from Rob. So, most likely the Renesas kernel maintainer(s), i.e. Simon,
> which differs from get_maintainers.pl of vendor-prefixes.txt.

Simon, do you think you can take this patch?

Thanks,
Fab

> 
> Regards,
> Andreas
> 
> >>> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >>> Sent: 16 January 2019 18:38
> >>> Subject: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon
> >>> Linux.
> >>>
> >>> From: Biju Das <biju.das@bp.renesas.com>
> >>>
> >>> Add Silicon Linux to the list of devicetree vendor prefixes.
> >>>
> >>> Website: http://www.si-linux.co.jp
> >>>
> >>> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> >>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >>> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> >>> ---
> >>>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> >>>  1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> >>> b/Documentation/devicetree/bindings/vendor-prefixes.txt index
> >>> 4b1a2a8..02a7037 100644 ---
> >>> a/Documentation/devicetree/bindings/vendor-prefixes.txt +++
> >>> b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -344,6
> >>> +344,7 @@ sgxSGX Sensortech sharpSharp Corporation
> >>>  shimafujiShimafuji Electric, Inc.
> >>>  si-enSi-En Technology Ltd.
> >>> +si-linuxSilicon Linux Corporation
> >>>  sifiveSiFive, Inc.
> >>>  sigmaSigma Designs, Inc.
> >>>  siiSeiko Instruments, Inc.
> >>> --
> >>> 2.7.4
> >>
> >>
> >>
> >> Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael
> >> Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf,
> >> Arcadiastrasse 10, 40472 Duesseldorf,
> >> Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708
> >> USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE
> >> reg. no.: DE 14978647
> >
> >
> >
> >
> > Best regards,
> >
> > Lukasz Majewski
> >
> > --
> >
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
> >
> 
> 
> --
> SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer, Jane Smithard, Graham Norton
> HRB 21284 (AG Nürnberg)

Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.

[Simon Horman]

On Fri, Mar 01, 2019 at 12:03:06PM +0000, Fabrizio Castro wrote:
> Thank you Andreas.
> 
> > From: Andreas Färber <afaerber@suse.de>
> > Sent: 15 February 2019 09:10
> > Subject: Re: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon Linux.
> > 
> > Hi Lukasz and Fabrizio,
> > 
> > Am 15.02.19 um 07:52 schrieb Lukasz Majewski:
> > > The best approach is to run:
> > >
> > > git format patch -1 <your patch sha>
> > >
> > > And then
> > >
> > > scripts/get_maintainer.pl 0001-xxxxxxx
> > >
> > > You shall see the the list of people to send the patch.
> > 
> > No, that does not answer his question. And please don't top-post.
> > 
> > >> Who is the best person for taking this patch?
> > 
> > The answer is: whomever is taking dt-bindings patches in the following
> > 10 patches that make use of this prefix, once you have a Reviewed-by
> > from Rob. So, most likely the Renesas kernel maintainer(s), i.e. Simon,
> > which differs from get_maintainers.pl of vendor-prefixes.txt.
> 
> Simon, do you think you can take this patch?

Sure, I have queued it up for v5.2.

> 
> Thanks,
> Fab
> 
> > 
> > Regards,
> > Andreas
> > 
> > >>> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >>> Sent: 16 January 2019 18:38
> > >>> Subject: [PATCH 01/11] dt-bindings: Add vendor prefix for Silicon
> > >>> Linux.
> > >>>
> > >>> From: Biju Das <biju.das@bp.renesas.com>
> > >>>
> > >>> Add Silicon Linux to the list of devicetree vendor prefixes.
> > >>>
> > >>> Website: http://www.si-linux.co.jp
> > >>>
> > >>> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > >>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >>> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > >>> ---
> > >>>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > >>>  1 file changed, 1 insertion(+)
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > >>> b/Documentation/devicetree/bindings/vendor-prefixes.txt index
> > >>> 4b1a2a8..02a7037 100644 ---
> > >>> a/Documentation/devicetree/bindings/vendor-prefixes.txt +++
> > >>> b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -344,6
> > >>> +344,7 @@ sgxSGX Sensortech sharpSharp Corporation
> > >>>  shimafujiShimafuji Electric, Inc.
> > >>>  si-enSi-En Technology Ltd.
> > >>> +si-linuxSilicon Linux Corporation
> > >>>  sifiveSiFive, Inc.
> > >>>  sigmaSigma Designs, Inc.
> > >>>  siiSeiko Instruments, Inc.
> > >>> --
> > >>> 2.7.4
> > >>
> > >>
> > >>
> > >> Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael
> > >> Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf,
> > >> Arcadiastrasse 10, 40472 Duesseldorf,
> > >> Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708
> > >> USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE
> > >> reg. no.: DE 14978647
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > > Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
> > >
> > 
> > 
> > --
> > SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> > GF: Felix Imendörffer, Jane Smithard, Graham Norton
> > HRB 21284 (AG Nürnberg)
> 

[PATCH 02/11] dt-bindings: arm: renesas: Add si-linux cat87[45] boards

[Fabrizio Castro]

This patch adds board cat874 (powered by the RZ/G2E) and board
cat875 (that sits on top of cat874). Both boards are made by
Silicon Linux.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index 5e9d486..9e1e07b 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -108,6 +108,14 @@ properties:
 
       - description: RZ/G2E (R8A774C0)
         items:
+          - enum:
+              - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
+          - const: renesas,r8a774c0
+
+      - items:
+          - enum:
+              - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
+          - const: si-linux,cat874
           - const: renesas,r8a774c0
 
       - description: R-Car M1A (R8A77781)
-- 
2.7.4

Re: [PATCH 02/11] dt-bindings: arm: renesas: Add si-linux cat87[45] boards

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:45PM +0000, Fabrizio Castro wrote:
> This patch adds board cat874 (powered by the RZ/G2E) and board
> cat875 (that sits on top of cat874). Both boards are made by
> Silicon Linux.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index 5e9d486..9e1e07b 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -108,6 +108,14 @@ properties:
>  
>        - description: RZ/G2E (R8A774C0)
>          items:
> +          - enum:
> +              - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)

Can I confirm that "96board platform" is correct for this board - I don't
see it in the documentation I have, but that may not mean much.


That aside, I'd like to wait for Rob to indicate if he will accept
patch 1, which adds si-linux as a vendor, before I apply this patch.

> +          - const: renesas,r8a774c0
> +
> +      - items:
> +          - enum:
> +              - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
> +          - const: si-linux,cat874
>            - const: renesas,r8a774c0
>  
>        - description: R-Car M1A (R8A77781)
> -- 
> 2.7.4
> 

RE: [PATCH 02/11] dt-bindings: arm: renesas: Add si-linux cat87[45] boards

[Chris Paterson]

Hello Simon,

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 January 2019 10:51
> 
> On Wed, Jan 16, 2019 at 06:37:45PM +0000, Fabrizio Castro wrote:
> > This patch adds board cat874 (powered by the RZ/G2E) and board
> > cat875 (that sits on top of cat874). Both boards are made by
> > Silicon Linux.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > ---
> >  Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml
> b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index 5e9d486..9e1e07b 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -108,6 +108,14 @@ properties:
> >
> >        - description: RZ/G2E (R8A774C0)
> >          items:
> > +          - enum:
> > +              - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
> 
> Can I confirm that "96board platform" is correct for this board - I don't
> see it in the documentation I have, but that may not mean much.

The board follows the extended version of the Linaro 96board consumer edition (CE) specification [1].

You can see a pretty picture of the board on the CIP Blog [2].

[1] https://www.96boards.org/specifications/
[2] https://www.cip-project.org/blog/2018/10/23/renesas-rz-g2m-96ce-board-adopted-as-arm64-reference-board-for-the-next-cip-slts-kernel

Kind regards, Chris

> 
> 
> That aside, I'd like to wait for Rob to indicate if he will accept
> patch 1, which adds si-linux as a vendor, before I apply this patch.
> 
> > +          - const: renesas,r8a774c0
> > +
> > +      - items:
> > +          - enum:
> > +              - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
> > +          - const: si-linux,cat874
> >            - const: renesas,r8a774c0
> >
> >        - description: R-Car M1A (R8A77781)
> > --
> > 2.7.4
> >

Re: [PATCH 02/11] dt-bindings: arm: renesas: Add si-linux cat87[45] boards

[Simon Horman]

On Thu, Jan 17, 2019 at 12:32:37PM +0000, Chris Paterson wrote:
> Hello Simon,
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 17 January 2019 10:51
> > 
> > On Wed, Jan 16, 2019 at 06:37:45PM +0000, Fabrizio Castro wrote:
> > > This patch adds board cat874 (powered by the RZ/G2E) and board
> > > cat875 (that sits on top of cat874). Both boards are made by
> > > Silicon Linux.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > > ---
> > >  Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
> > >  1 file changed, 8 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml
> > b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > index 5e9d486..9e1e07b 100644
> > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > @@ -108,6 +108,14 @@ properties:
> > >
> > >        - description: RZ/G2E (R8A774C0)
> > >          items:
> > > +          - enum:
> > > +              - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
> > 
> > Can I confirm that "96board platform" is correct for this board - I don't
> > see it in the documentation I have, but that may not mean much.
> 
> The board follows the extended version of the Linaro 96board consumer edition (CE) specification [1].
> 
> You can see a pretty picture of the board on the CIP Blog [2].
> 
> [1] https://www.96boards.org/specifications/
> [2] https://www.cip-project.org/blog/2018/10/23/renesas-rz-g2m-96ce-board-adopted-as-arm64-reference-board-for-the-next-cip-slts-kernel

Thanks Chris, in that case I am fine with this patch.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> > That aside, I'd like to wait for Rob to indicate if he will accept
> > patch 1, which adds si-linux as a vendor, before I apply this patch.
> > 
> > > +          - const: renesas,r8a774c0
> > > +
> > > +      - items:
> > > +          - enum:
> > > +              - si-linux,cat875 # Silicon Linux sub board for CAT874 (CAT875)
> > > +          - const: si-linux,cat874
> > >            - const: renesas,r8a774c0
> > >
> > >        - description: R-Car M1A (R8A77781)
> > > --
> > > 2.7.4
> > >
> 

Re: [PATCH 02/11] dt-bindings: arm: renesas: Add si-linux cat87[45] boards

[Simon Horman]

On Thu, Jan 17, 2019 at 01:59:12PM +0100, Simon Horman wrote:
> On Thu, Jan 17, 2019 at 12:32:37PM +0000, Chris Paterson wrote:
> > Hello Simon,
> > 
> > > From: Simon Horman <horms@verge.net.au>
> > > Sent: 17 January 2019 10:51
> > > 
> > > On Wed, Jan 16, 2019 at 06:37:45PM +0000, Fabrizio Castro wrote:
> > > > This patch adds board cat874 (powered by the RZ/G2E) and board
> > > > cat875 (that sits on top of cat874). Both boards are made by
> > > > Silicon Linux.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
> > > >  1 file changed, 8 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > index 5e9d486..9e1e07b 100644
> > > > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > > @@ -108,6 +108,14 @@ properties:
> > > >
> > > >        - description: RZ/G2E (R8A774C0)
> > > >          items:
> > > > +          - enum:
> > > > +              - si-linux,cat874 # Silicon Linux RZ/G2E 96board platform (CAT874)
> > > 
> > > Can I confirm that "96board platform" is correct for this board - I don't
> > > see it in the documentation I have, but that may not mean much.
> > 
> > The board follows the extended version of the Linaro 96board consumer edition (CE) specification [1].
> > 
> > You can see a pretty picture of the board on the CIP Blog [2].
> > 
> > [1] https://www.96boards.org/specifications/
> > [2] https://www.cip-project.org/blog/2018/10/23/renesas-rz-g2m-96ce-board-adopted-as-arm64-reference-board-for-the-next-cip-slts-kernel
> 
> Thanks Chris, in that case I am fine with this patch.
> 
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> 
> > > That aside, I'd like to wait for Rob to indicate if he will accept
> > > patch 1, which adds si-linux as a vendor, before I apply this patch.

It appears that the use of si-linux as a vendor name.
Accordingly I have applied this patch for v5.1.

...

[PATCH 03/11] arm64: dts: renesas: Add Si-Linux CAT874 board support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

Basic support for the Si-Linux board based on RZ/G2E:
  - Memory,
  - Main crystal,
  - Serial console

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile            |  1 +
 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index a8ce659..11997d7 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
new file mode 100644
index 0000000..6eababc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774c0.dtsi"
+
+/ {
+	model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
+	compatible = "si-linux,cat874", "renesas,r8a774c0";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&scif2 {
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH 03/11] arm64: dts: renesas: Add Si-Linux CAT874 board support

[Geert Uytterhoeven]

On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> From: Biju Das <biju.das@bp.renesas.com>
>
> Basic support for the Si-Linux board based on RZ/G2E:
>   - Memory,
>   - Main crystal,
>   - Serial console
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Pending acceptance of the DT bindings
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts

> +       chosen {
> +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";

FWIW, the root and ip parameters won't do anything, until you add network
support.

> +               stdout-path = "serial0:115200n8";
> +       };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 03/11] arm64: dts: renesas: Add Si-Linux CAT874 board support

[Simon Horman]

On Thu, Jan 17, 2019 at 12:04:51PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > Basic support for the Si-Linux board based on RZ/G2E:
> >   - Memory,
> >   - Main crystal,
> >   - Serial console
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> 
> Pending acceptance of the DT bindings
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

I have applied the binding patch locally and intend to include
it in my next push. With that in mind I have also applied this patch
for v5.1.

> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> 
> > +       chosen {
> > +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
> 
> FWIW, the root and ip parameters won't do anything, until you add network
> support.

True, but I don't think that warrants a respin.

> 
> > +               stdout-path = "serial0:115200n8";
> > +       };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> 

[PATCH 04/11] arm64: dts: renesas: Add Si-Linux EK874 board support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

The EK874 development kit from Silicon Linux is made of CAT874 (the main
board) and CAT875 (the sub board that goes on top of CAT874).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile           |  2 +-
 arch/arm64/boot/dts/renesas/cat875.dtsi        | 10 ++++++++++
 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 14 ++++++++++++++
 3 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/renesas/cat875.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 11997d7..6cde526 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
+dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
new file mode 100644
index 0000000..a41d0d8
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/ {
+	model = "Silicon Linux sub board for CAT874 (CAT875)";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
new file mode 100644
index 0000000..e7b6619
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+#include "r8a774c0-cat874.dts"
+#include "cat875.dtsi"
+
+/ {
+	model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
+	compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
+};
-- 
2.7.4

Re: [PATCH 04/11] arm64: dts: renesas: Add Si-Linux EK874 board support

[Geert Uytterhoeven]

On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> From: Biju Das <biju.das@bp.renesas.com>
>
> The EK874 development kit from Silicon Linux is made of CAT874 (the main
> board) and CAT875 (the sub board that goes on top of CAT874).
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Pending acceptance of the DT bindings
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/11] arm64: dts: renesas: Add Si-Linux EK874 board support

[Simon Horman]

On Thu, Jan 17, 2019 at 12:05:59PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > The EK874 development kit from Silicon Linux is made of CAT874 (the main
> > board) and CAT875 (the sub board that goes on top of CAT874).
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> 
> Pending acceptance of the DT bindings
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied for v5.1.

[PATCH 05/11] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

This patch adds pincontrol support to scif2.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 6eababc..c545ce5 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -32,6 +32,16 @@
 	clock-frequency = <48000000>;
 };
 
+&pfc {
+	scif2_pins: scif2 {
+		groups = "scif2_data_a";
+		function = "scif2";
+	};
+};
+
 &scif2 {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
 	status = "okay";
 };
-- 
2.7.4

Re: [PATCH 05/11] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2

[Geert Uytterhoeven]

On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> From: Biju Das <biju.das@bp.renesas.com>
>
> This patch adds pincontrol support to scif2.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/11] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2

[Simon Horman]

On Thu, Jan 17, 2019 at 12:06:39PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 16, 2019 at 7:38 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > This patch adds pincontrol support to scif2.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied for v5.1.

[PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

This patch adds uSD card support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 50 +++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index c545ce5..477a56b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "r8a774c0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
@@ -26,6 +27,29 @@
 		/* first 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};
+
+	vcc_sdhi0: regulator-vcc-sdhi0 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDHI0 Vcc";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 1
+			  1800000 0>;
+	};
 };
 
 &extal_clk {
@@ -37,6 +61,18 @@
 		groups = "scif2_data_a";
 		function = "scif2";
 	};
+
+	sdhi0_pins: sd0 {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
+	};
 };
 
 &scif2 {
@@ -45,3 +81,17 @@
 
 	status = "okay";
 };
+
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&vcc_sdhi0>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:49PM +0000, Fabrizio Castro wrote:
> From: Biju Das <biju.das@bp.renesas.com>
> 
> This patch adds uSD card support.

Can I confirm that SDHI0 is wired up to a uSD slot?

I ask because if that is the case then this patch looks good to me.
But if it is wired up to a full-size SD slot then I believe
a wp-gpio (write protect) should be described.

> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 50 +++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> index c545ce5..477a56b 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> @@ -7,6 +7,7 @@
>  
>  /dts-v1/;
>  #include "r8a774c0.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>  
>  / {
>  	model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
> @@ -26,6 +27,29 @@
>  		/* first 128MB is reserved for secure area. */
>  		reg = <0x0 0x48000000 0x0 0x78000000>;
>  	};
> +
> +	vcc_sdhi0: regulator-vcc-sdhi0 {
> +		compatible = "regulator-fixed";
> +
> +		regulator-name = "SDHI0 Vcc";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-always-on;
> +		regulator-boot-on;
> +	};
> +
> +	vccq_sdhi0: regulator-vccq-sdhi0 {
> +		compatible = "regulator-gpio";
> +
> +		regulator-name = "SDHI0 VccQ";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> +		gpios-states = <1>;
> +		states = <3300000 1
> +			  1800000 0>;
> +	};
>  };
>  
>  &extal_clk {
> @@ -37,6 +61,18 @@
>  		groups = "scif2_data_a";
>  		function = "scif2";
>  	};
> +
> +	sdhi0_pins: sd0 {
> +		groups = "sdhi0_data4", "sdhi0_ctrl";
> +		function = "sdhi0";
> +		power-source = <3300>;
> +	};
> +
> +	sdhi0_pins_uhs: sd0_uhs {
> +		groups = "sdhi0_data4", "sdhi0_ctrl";
> +		function = "sdhi0";
> +		power-source = <1800>;
> +	};
>  };
>  
>  &scif2 {
> @@ -45,3 +81,17 @@
>  
>  	status = "okay";
>  };
> +
> +&sdhi0 {
> +	pinctrl-0 = <&sdhi0_pins>;
> +	pinctrl-1 = <&sdhi0_pins_uhs>;
> +	pinctrl-names = "default", "state_uhs";
> +
> +	vmmc-supply = <&vcc_sdhi0>;
> +	vqmmc-supply = <&vccq_sdhi0>;
> +	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
> +	bus-width = <4>;
> +	sd-uhs-sdr50;
> +	sd-uhs-sdr104;
> +	status = "okay";
> +};
> -- 
> 2.7.4
> 

RE: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 January 2019 11:12
> Subject: Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support
>
> On Wed, Jan 16, 2019 at 06:37:49PM +0000, Fabrizio Castro wrote:
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > This patch adds uSD card support.
>
> Can I confirm that SDHI0 is wired up to a uSD slot?

Yes, it is wired up to a uSD slot

Thanks,
Fab

>
> I ask because if that is the case then this patch looks good to me.
> But if it is wired up to a full-size SD slot then I believe
> a wp-gpio (write protect) should be described.
>
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 50 +++++++++++++++++++++++++
> >  1 file changed, 50 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> > index c545ce5..477a56b 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
> > @@ -7,6 +7,7 @@
> >
> >  /dts-v1/;
> >  #include "r8a774c0.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> >
> >  / {
> >  model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
> > @@ -26,6 +27,29 @@
> >  /* first 128MB is reserved for secure area. */
> >  reg = <0x0 0x48000000 0x0 0x78000000>;
> >  };
> > +
> > +vcc_sdhi0: regulator-vcc-sdhi0 {
> > +compatible = "regulator-fixed";
> > +
> > +regulator-name = "SDHI0 Vcc";
> > +regulator-min-microvolt = <3300000>;
> > +regulator-max-microvolt = <3300000>;
> > +regulator-always-on;
> > +regulator-boot-on;
> > +};
> > +
> > +vccq_sdhi0: regulator-vccq-sdhi0 {
> > +compatible = "regulator-gpio";
> > +
> > +regulator-name = "SDHI0 VccQ";
> > +regulator-min-microvolt = <1800000>;
> > +regulator-max-microvolt = <3300000>;
> > +
> > +gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> > +gpios-states = <1>;
> > +states = <3300000 1
> > +  1800000 0>;
> > +};
> >  };
> >
> >  &extal_clk {
> > @@ -37,6 +61,18 @@
> >  groups = "scif2_data_a";
> >  function = "scif2";
> >  };
> > +
> > +sdhi0_pins: sd0 {
> > +groups = "sdhi0_data4", "sdhi0_ctrl";
> > +function = "sdhi0";
> > +power-source = <3300>;
> > +};
> > +
> > +sdhi0_pins_uhs: sd0_uhs {
> > +groups = "sdhi0_data4", "sdhi0_ctrl";
> > +function = "sdhi0";
> > +power-source = <1800>;
> > +};
> >  };
> >
> >  &scif2 {
> > @@ -45,3 +81,17 @@
> >
> >  status = "okay";
> >  };
> > +
> > +&sdhi0 {
> > +pinctrl-0 = <&sdhi0_pins>;
> > +pinctrl-1 = <&sdhi0_pins_uhs>;
> > +pinctrl-names = "default", "state_uhs";
> > +
> > +vmmc-supply = <&vcc_sdhi0>;
> > +vqmmc-supply = <&vccq_sdhi0>;
> > +cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
> > +bus-width = <4>;
> > +sd-uhs-sdr50;
> > +sd-uhs-sdr104;
> > +status = "okay";
> > +};
> > --
> > 2.7.4
> >



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support

[Simon Horman]

On Thu, Jan 17, 2019 at 01:19:06PM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 17 January 2019 11:12
> > Subject: Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support
> >
> > On Wed, Jan 16, 2019 at 06:37:49PM +0000, Fabrizio Castro wrote:
> > > From: Biju Das <biju.das@bp.renesas.com>
> > >
> > > This patch adds uSD card support.
> >
> > Can I confirm that SDHI0 is wired up to a uSD slot?
> 
> Yes, it is wired up to a uSD slot

Thanks for the conformation.

Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support

[Simon Horman]

On Sun, Jan 20, 2019 at 09:28:00AM +0100, Simon Horman wrote:
> On Thu, Jan 17, 2019 at 01:19:06PM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> > 
> > Thank you for your feedback!
> > 
> > > From: Simon Horman <horms@verge.net.au>
> > > Sent: 17 January 2019 11:12
> > > Subject: Re: [PATCH 06/11] arm64: dts: renesas: r8a774c0-cat874: Add uSD support
> > >
> > > On Wed, Jan 16, 2019 at 06:37:49PM +0000, Fabrizio Castro wrote:
> > > > From: Biju Das <biju.das@bp.renesas.com>
> > > >
> > > > This patch adds uSD card support.
> > >
> > > Can I confirm that SDHI0 is wired up to a uSD slot?
> > 
> > Yes, it is wired up to a uSD slot
> 
> Thanks for the conformation.

I have now applied this for v5.1.

[PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support

[Fabrizio Castro]

From: Biju Das <biju.das@bp.renesas.com>

This patch adds ethernet support to the sub board.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index a41d0d8..805ffa7 100644
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -7,4 +7,34 @@
 
 / {
 	model = "Silicon Linux sub board for CAT874 (CAT875)";
+
+	aliases {
+		ethernet0 = &avb;
+	};
+};
+
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pfc {
+	avb_pins: avb {
+		mux {
+			groups = "avb_mii";
+			function = "avb";
+		};
+	};
 };
-- 
2.7.4

Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:50PM +0000, Fabrizio Castro wrote:
> From: Biju Das <biju.das@bp.renesas.com>
> 
> This patch adds ethernet support to the sub board.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
> index a41d0d8..805ffa7 100644
> --- a/arch/arm64/boot/dts/renesas/cat875.dtsi
> +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
> @@ -7,4 +7,34 @@
>  
>  / {
>  	model = "Silicon Linux sub board for CAT874 (CAT875)";
> +
> +	aliases {
> +		ethernet0 = &avb;
> +	};
> +};
> +
> +&avb {
> +	pinctrl-0 = <&avb_pins>;
> +	pinctrl-names = "default";
> +	renesas,no-ether-link;

Is the renesas,no-ether-link required?

My understanding is that "the property should only be used when a
board does not provide a proper AVB_LINK signal". And from my reading
of the schematic it looks like that signal may be provided on this board.

That said, I have an outstanding patch for this for E3/Ebisu which
I have not applied because I am unsure of its correctness.

[PATCH] arm64: dts: renesas: ebisu: Remove renesas, no-ether-link property
https://patchwork.kernel.org/patch/10692755/

Similar patches have been applied for other boards.
f.e:

[PATCH] arm64: dts: renesas: salvator-x: Remove renesas, no-ether-link property
https://git.kernel.org/torvalds/c/87c059e9c39d

> +	phy-handle = <&phy0>;
> +	phy-mode = "rgmii";
> +	status = "okay";
> +
> +	phy0: ethernet-phy@0 {
> +		rxc-skew-ps = <1500>;
> +		reg = <0>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> +		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> +	};
> +};
> +
> +&pfc {
> +	avb_pins: avb {
> +		mux {
> +			groups = "avb_mii";
> +			function = "avb";
> +		};
> +	};
>  };
> -- 
> 2.7.4
> 

RE: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support

[Fabrizio Castro]

Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 17 January 2019 12:00
> Subject: Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support
>
> On Wed, Jan 16, 2019 at 06:37:50PM +0000, Fabrizio Castro wrote:
> > From: Biju Das <biju.das@bp.renesas.com>
> >
> > This patch adds ethernet support to the sub board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > index a41d0d8..805ffa7 100644
> > --- a/arch/arm64/boot/dts/renesas/cat875.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > @@ -7,4 +7,34 @@
> >
> >  / {
> >  model = "Silicon Linux sub board for CAT874 (CAT875)";
> > +
> > +aliases {
> > +ethernet0 = &avb;
> > +};
> > +};
> > +
> > +&avb {
> > +pinctrl-0 = <&avb_pins>;
> > +pinctrl-names = "default";
> > +renesas,no-ether-link;
>
> Is the renesas,no-ether-link required?

The AVB_LINK pin from the SoC is connected to the PMEB (Power Management Event, B stands for
active low) pin on the  PHY, which means it is not a link signal. The PMEB signal is active when a magic
packet or a wake up frame are detected. As a result, we need renesas,no-ether-link and we can't
specify avb_link with avb_pin either.

Thanks,
Fab

>
> My understanding is that "the property should only be used when a
> board does not provide a proper AVB_LINK signal". And from my reading
> of the schematic it looks like that signal may be provided on this board.
>
> That said, I have an outstanding patch for this for E3/Ebisu which
> I have not applied because I am unsure of its correctness.
>
> [PATCH] arm64: dts: renesas: ebisu: Remove renesas, no-ether-link property
> https://patchwork.kernel.org/patch/10692755/
>
> Similar patches have been applied for other boards.
> f.e:
>
> [PATCH] arm64: dts: renesas: salvator-x: Remove renesas, no-ether-link property
> https://git.kernel.org/torvalds/c/87c059e9c39d
>
> > +phy-handle = <&phy0>;
> > +phy-mode = "rgmii";
> > +status = "okay";
> > +
> > +phy0: ethernet-phy@0 {
> > +rxc-skew-ps = <1500>;
> > +reg = <0>;
> > +interrupt-parent = <&gpio2>;
> > +interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> > +reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> > +};
> > +};
> > +
> > +&pfc {
> > +avb_pins: avb {
> > +mux {
> > +groups = "avb_mii";
> > +function = "avb";
> > +};
> > +};
> >  };
> > --
> > 2.7.4
> >



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support

[Simon Horman]

On Thu, Jan 17, 2019 at 01:27:51PM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> Thank you for your feedback!
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 17 January 2019 12:00
> > Subject: Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support
> >
> > On Wed, Jan 16, 2019 at 06:37:50PM +0000, Fabrizio Castro wrote:
> > > From: Biju Das <biju.das@bp.renesas.com>
> > >
> > > This patch adds ethernet support to the sub board.
> > >
> > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
> > >  1 file changed, 30 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > index a41d0d8..805ffa7 100644
> > > --- a/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > @@ -7,4 +7,34 @@
> > >
> > >  / {
> > >  model = "Silicon Linux sub board for CAT874 (CAT875)";
> > > +
> > > +aliases {
> > > +ethernet0 = &avb;
> > > +};
> > > +};
> > > +
> > > +&avb {
> > > +pinctrl-0 = <&avb_pins>;
> > > +pinctrl-names = "default";
> > > +renesas,no-ether-link;
> >
> > Is the renesas,no-ether-link required?
> 
> The AVB_LINK pin from the SoC is connected to the PMEB (Power Management Event, B stands for
> active low) pin on the  PHY, which means it is not a link signal. The PMEB signal is active when a magic
> packet or a wake up frame are detected. As a result, we need renesas,no-ether-link and we can't
> specify avb_link with avb_pin either.

Thanks for following-up. In that case I am fine with this patch.

Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support

[Simon Horman]

On Sun, Jan 20, 2019 at 09:28:45AM +0100, Simon Horman wrote:
> On Thu, Jan 17, 2019 at 01:27:51PM +0000, Fabrizio Castro wrote:
> > Hello Simon,
> > 
> > Thank you for your feedback!
> > 
> > > From: Simon Horman <horms@verge.net.au>
> > > Sent: 17 January 2019 12:00
> > > Subject: Re: [PATCH 07/11] arm64: dts: renesas: cat875: Add ethernet support
> > >
> > > On Wed, Jan 16, 2019 at 06:37:50PM +0000, Fabrizio Castro wrote:
> > > > From: Biju Das <biju.das@bp.renesas.com>
> > > >
> > > > This patch adds ethernet support to the sub board.
> > > >
> > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
> > > >  1 file changed, 30 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > > index a41d0d8..805ffa7 100644
> > > > --- a/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
> > > > @@ -7,4 +7,34 @@
> > > >
> > > >  / {
> > > >  model = "Silicon Linux sub board for CAT874 (CAT875)";
> > > > +
> > > > +aliases {
> > > > +ethernet0 = &avb;
> > > > +};
> > > > +};
> > > > +
> > > > +&avb {
> > > > +pinctrl-0 = <&avb_pins>;
> > > > +pinctrl-names = "default";
> > > > +renesas,no-ether-link;
> > >
> > > Is the renesas,no-ether-link required?
> > 
> > The AVB_LINK pin from the SoC is connected to the PMEB (Power Management Event, B stands for
> > active low) pin on the  PHY, which means it is not a link signal. The PMEB signal is active when a magic
> > packet or a wake up frame are detected. As a result, we need renesas,no-ether-link and we can't
> > specify avb_link with avb_pin either.
> 
> Thanks for following-up. In that case I am fine with this patch.
> 

Thanks again, applied for v5.1.

[PATCH 08/11] clk: renesas: r8a774c0: Add missing CANFD clock

[Fabrizio Castro]

This patch adds the missing CANFD clock to the r8a774c0 specific
clock driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 drivers/clk/renesas/r8a774c0-cpg-mssr.c       |  4 ++++
 include/dt-bindings/clock/r8a774c0-cpg-mssr.h | 17 +++++++++--------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 10b9689..28bcc81 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -33,6 +33,7 @@ enum clk_ids {
 	CLK_PLL1,
 	CLK_PLL3,
 	CLK_PLL0D4,
+	CLK_PLL0D6,
 	CLK_PLL0D8,
 	CLK_PLL0D20,
 	CLK_PLL0D24,
@@ -61,6 +62,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
 
 	DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,	   1, 100),
 	DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),
+	DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),
 	DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),
 	DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),
 	DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
@@ -112,6 +114,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
 	DEF_GEN3_PE("s3d2c",   R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
 	DEF_GEN3_PE("s3d4c",   R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
 
+	DEF_DIV6P1("canfd",    R8A774C0_CLK_CANFD, CLK_PLL0D6, 0x244),
 	DEF_DIV6P1("csi0",     R8A774C0_CLK_CSI0,  CLK_PLL1D2, 0x00c),
 	DEF_DIV6P1("mso",      R8A774C0_CLK_MSO,   CLK_PLL1D2, 0x014),
 
@@ -187,6 +190,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
 	DEF_MOD("gpio2",		 910,	R8A774C0_CLK_S3D4),
 	DEF_MOD("gpio1",		 911,	R8A774C0_CLK_S3D4),
 	DEF_MOD("gpio0",		 912,	R8A774C0_CLK_S3D4),
+	DEF_MOD("can-fd",		 914,	R8A774C0_CLK_S3D2),
 	DEF_MOD("can-if1",		 915,	R8A774C0_CLK_S3D4),
 	DEF_MOD("can-if0",		 916,	R8A774C0_CLK_S3D4),
 	DEF_MOD("i2c6",			 918,	R8A774C0_CLK_S3D2),
diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
index 8fe51b6..f269ce3 100644
--- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
@@ -48,13 +48,14 @@
 #define R8A774C0_CLK_ZA2		37
 #define R8A774C0_CLK_ZA8		38
 #define R8A774C0_CLK_Z2D		39
-#define R8A774C0_CLK_MSO		40
-#define R8A774C0_CLK_R			41
-#define R8A774C0_CLK_OSC		42
-#define R8A774C0_CLK_LV0		43
-#define R8A774C0_CLK_LV1		44
-#define R8A774C0_CLK_CSI0		45
-#define R8A774C0_CLK_CP			46
-#define R8A774C0_CLK_CPEX		47
+#define R8A774C0_CLK_CANFD		40
+#define R8A774C0_CLK_MSO		41
+#define R8A774C0_CLK_R			42
+#define R8A774C0_CLK_OSC		43
+#define R8A774C0_CLK_LV0		44
+#define R8A774C0_CLK_LV1		45
+#define R8A774C0_CLK_CSI0		46
+#define R8A774C0_CLK_CP			47
+#define R8A774C0_CLK_CPEX		48
 
 #endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
-- 
2.7.4

Re: [PATCH 08/11] clk: renesas: r8a774c0: Add missing CANFD clock

[Geert Uytterhoeven]

Hi Fabrizio,

Thanks for your patch!

On Wed, Jan 16, 2019 at 7:39 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> This patch adds the missing CANFD clock to the r8a774c0 specific
> clock driver.

Are you sure the CANFD clock exists on RZ/G2E?

> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c

> --- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
> +++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
> @@ -48,13 +48,14 @@
>  #define R8A774C0_CLK_ZA2               37
>  #define R8A774C0_CLK_ZA8               38
>  #define R8A774C0_CLK_Z2D               39
> -#define R8A774C0_CLK_MSO               40
> -#define R8A774C0_CLK_R                 41
> -#define R8A774C0_CLK_OSC               42
> -#define R8A774C0_CLK_LV0               43
> -#define R8A774C0_CLK_LV1               44
> -#define R8A774C0_CLK_CSI0              45
> -#define R8A774C0_CLK_CP                        46
> -#define R8A774C0_CLK_CPEX              47
> +#define R8A774C0_CLK_CANFD             40
> +#define R8A774C0_CLK_MSO               41
> +#define R8A774C0_CLK_R                 42
> +#define R8A774C0_CLK_OSC               43
> +#define R8A774C0_CLK_LV0               44
> +#define R8A774C0_CLK_LV1               45
> +#define R8A774C0_CLK_CSI0              46
> +#define R8A774C0_CLK_CP                        47
> +#define R8A774C0_CLK_CPEX              48

This file is part of the DT ABI, hence list of definitions is append-only.

Please add R8A774C0_CLK_CANFD at the end, i.e.

    #define R8A774C0_CLK_CANFD              48

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 08/11] clk: renesas: r8a774c0: Add missing CANFD clock

[Fabrizio Castro]

Hi Geert,

Thank you for your feedback!

> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 16 January 2019 19:06
> Subject: Re: [PATCH 08/11] clk: renesas: r8a774c0: Add missing CANFD clock
>
> Hi Fabrizio,
>
> Thanks for your patch!
>
> On Wed, Jan 16, 2019 at 7:39 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > This patch adds the missing CANFD clock to the r8a774c0 specific
> > clock driver.
>
> Are you sure the CANFD clock exists on RZ/G2E?

I yet have to run tests on the board specific to CANFD, but we know for sure that's
going to appear on the RZ/G2E (if it's not in the revision of the SoC we have already).
Japan have confirmed that everything CANFD-wise should be the same as per the
corresponding Gen3 parts, and that's why are pushing this patch (and shortly
something similar for the r8a774a1) for it as it's on our critical path. Anyways, the
HW of the EK874 should support CANFD properly, therefore I am going to try and
run some tests (as soon as I sort out the cables), so that we clear any doubts.

Would you rather we held back all of the CAN related changes for now?

>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
>
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
>
> > --- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
> > +++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
> > @@ -48,13 +48,14 @@
> >  #define R8A774C0_CLK_ZA2               37
> >  #define R8A774C0_CLK_ZA8               38
> >  #define R8A774C0_CLK_Z2D               39
> > -#define R8A774C0_CLK_MSO               40
> > -#define R8A774C0_CLK_R                 41
> > -#define R8A774C0_CLK_OSC               42
> > -#define R8A774C0_CLK_LV0               43
> > -#define R8A774C0_CLK_LV1               44
> > -#define R8A774C0_CLK_CSI0              45
> > -#define R8A774C0_CLK_CP                        46
> > -#define R8A774C0_CLK_CPEX              47
> > +#define R8A774C0_CLK_CANFD             40
> > +#define R8A774C0_CLK_MSO               41
> > +#define R8A774C0_CLK_R                 42
> > +#define R8A774C0_CLK_OSC               43
> > +#define R8A774C0_CLK_LV0               44
> > +#define R8A774C0_CLK_LV1               45
> > +#define R8A774C0_CLK_CSI0              46
> > +#define R8A774C0_CLK_CP                        47
> > +#define R8A774C0_CLK_CPEX              48
>
> This file is part of the DT ABI, hence list of definitions is append-only.

Will fix this with a v2

Thanks,
Fab

>
> Please add R8A774C0_CLK_CANFD at the end, i.e.
>
>     #define R8A774C0_CLK_CANFD              48
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

[Fabrizio Castro]

According to the latest information, the clock options for CAN on RZ/G2
are the same as the ones available on R-Car Gen3

Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index 7fcf501..b463e12 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -28,13 +28,8 @@ Required properties:
 
 - reg: physical base address and size of the R-Car CAN register map.
 - interrupts: interrupt specifier for the sole interrupt.
-- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2
-	  devices.
-	  phandles and clock specifiers for 3 CAN clock inputs for every other
-	  SoC.
-- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
-	       3 clock input name strings for every other SoC: "clkp1", "clkp2",
-	       "can_clk".
+- clocks: phandles and clock specifiers for 3 CAN clock inputs.
+- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
 - pinctrl-0: pin control group to be used for this controller.
 - pinctrl-names: must be "default".
 
@@ -50,8 +45,7 @@ using the below properties:
 Optional properties:
 - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
 			    <0x0> (default) : Peripheral clock (clkp1)
-			    <0x1> : Peripheral clock (clkp2) (not supported by
-				    RZ/G2 devices)
+			    <0x1> : Peripheral clock (clkp2)
 			    <0x3> : External input clock
 
 Example
-- 
2.7.4

Re: [PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:52PM +0000, Fabrizio Castro wrote:
> According to the latest information, the clock options for CAN on RZ/G2
> are the same as the ones available on R-Car Gen3

I'm taking your word for the above.
As the patch matches the description:

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
> index 7fcf501..b463e12 100644
> --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
> @@ -28,13 +28,8 @@ Required properties:
>  
>  - reg: physical base address and size of the R-Car CAN register map.
>  - interrupts: interrupt specifier for the sole interrupt.
> -- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2
> -	  devices.
> -	  phandles and clock specifiers for 3 CAN clock inputs for every other
> -	  SoC.
> -- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
> -	       3 clock input name strings for every other SoC: "clkp1", "clkp2",
> -	       "can_clk".
> +- clocks: phandles and clock specifiers for 3 CAN clock inputs.
> +- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
>  - pinctrl-0: pin control group to be used for this controller.
>  - pinctrl-names: must be "default".
>  
> @@ -50,8 +45,7 @@ using the below properties:
>  Optional properties:
>  - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
>  			    <0x0> (default) : Peripheral clock (clkp1)
> -			    <0x1> : Peripheral clock (clkp2) (not supported by
> -				    RZ/G2 devices)
> +			    <0x1> : Peripheral clock (clkp2)
>  			    <0x3> : External input clock
>  
>  Example
> -- 
> 2.7.4
> 

Re: [PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

[Rob Herring]

On Wed, 16 Jan 2019 18:37:52 +0000, Fabrizio Castro wrote:
> According to the latest information, the clock options for CAN on RZ/G2
> are the same as the ones available on R-Car Gen3
> 
> Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks

[Fabrizio Castro]

Hello Marc,

I am sorry to bother you.
Do you think you can take this patch?

Thanks,
Fab

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Sent: 16 January 2019 18:38
> Subject: [PATCH 09/11] dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks
> 
> According to the latest information, the clock options for CAN on RZ/G2
> are the same as the ones available on R-Car Gen3
> 
> Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
>  Documentation/devicetree/bindings/net/can/rcar_can.txt | 12 +++---------
>  1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
> index 7fcf501..b463e12 100644
> --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
> @@ -28,13 +28,8 @@ Required properties:
> 
>  - reg: physical base address and size of the R-Car CAN register map.
>  - interrupts: interrupt specifier for the sole interrupt.
> -- clocks: phandles and clock specifiers for 2 CAN clock inputs for RZ/G2
> -	  devices.
> -	  phandles and clock specifiers for 3 CAN clock inputs for every other
> -	  SoC.
> -- clock-names: 2 clock input name strings for RZ/G2: "clkp1", "can_clk".
> -	       3 clock input name strings for every other SoC: "clkp1", "clkp2",
> -	       "can_clk".
> +- clocks: phandles and clock specifiers for 3 CAN clock inputs.
> +- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
>  - pinctrl-0: pin control group to be used for this controller.
>  - pinctrl-names: must be "default".
> 
> @@ -50,8 +45,7 @@ using the below properties:
>  Optional properties:
>  - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
>  			    <0x0> (default) : Peripheral clock (clkp1)
> -			    <0x1> : Peripheral clock (clkp2) (not supported by
> -				    RZ/G2 devices)
> +			    <0x1> : Peripheral clock (clkp2)
>  			    <0x3> : External input clock
> 
>  Example
> --
> 2.7.4

[PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes

[Fabrizio Castro]

According to the latest information, clkp2 is available on RZ/G2.
Modify CAN0 and CAN1 nodes accordingly.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 3970aaf..326ab3a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -809,8 +809,10 @@
 				     "renesas,rcar-gen3-can";
 			reg = <0 0xe6c30000 0 0x1000>;
 			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
-			clock-names = "clkp1", "can_clk";
+			clocks = <&cpg CPG_MOD 916>,
+				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 			resets = <&cpg 916>;
 			status = "disabled";
@@ -821,8 +823,10 @@
 				     "renesas,rcar-gen3-can";
 			reg = <0 0xe6c38000 0 0x1000>;
 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
-			clock-names = "clkp1", "can_clk";
+			clocks = <&cpg CPG_MOD 915>,
+				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
+				 <&can_clk>;
+			clock-names = "clkp1", "clkp2", "can_clk";
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 			resets = <&cpg 915>;
 			status = "disabled";
-- 
2.7.4

Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote:
> According to the latest information, clkp2 is available on RZ/G2.
> Modify CAN0 and CAN1 nodes accordingly.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Taking your word for the motivation for this change,
this patch seems fine to me but I would like to wait for review
from others.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> ---
>  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> index 3970aaf..326ab3a 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> @@ -809,8 +809,10 @@
>  				     "renesas,rcar-gen3-can";
>  			reg = <0 0xe6c30000 0 0x1000>;
>  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> -			clock-names = "clkp1", "can_clk";
> +			clocks = <&cpg CPG_MOD 916>,
> +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> +				 <&can_clk>;
> +			clock-names = "clkp1", "clkp2", "can_clk";
>  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
>  			resets = <&cpg 916>;
>  			status = "disabled";
> @@ -821,8 +823,10 @@
>  				     "renesas,rcar-gen3-can";
>  			reg = <0 0xe6c38000 0 0x1000>;
>  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> -			clock-names = "clkp1", "can_clk";
> +			clocks = <&cpg CPG_MOD 915>,
> +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> +				 <&can_clk>;
> +			clock-names = "clkp1", "clkp2", "can_clk";
>  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
>  			resets = <&cpg 915>;
>  			status = "disabled";
> -- 
> 2.7.4
> 

Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes

[Simon Horman]

On Thu, Jan 17, 2019 at 01:05:42PM +0100, Simon Horman wrote:
> On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote:
> > According to the latest information, clkp2 is available on RZ/G2.
> > Modify CAN0 and CAN1 nodes accordingly.
> > 
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> 
> Taking your word for the motivation for this change,
> this patch seems fine to me but I would like to wait for review
> from others.
> 
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

I am marking this as deferred until R8A774C0_CLK_CANFD
shows up in an rc release.

Alternatively I'd be happy to take a version that uses
numeric values, followed up by a patch to switching to R8A774C0_CLK_CANFD
once it is available in an rc release.

Please repost or otherwise ping me as appropriate.

> 
> > ---
> >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > index 3970aaf..326ab3a 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > @@ -809,8 +809,10 @@
> >  				     "renesas,rcar-gen3-can";
> >  			reg = <0 0xe6c30000 0 0x1000>;
> >  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> > -			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> > -			clock-names = "clkp1", "can_clk";
> > +			clocks = <&cpg CPG_MOD 916>,
> > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > +				 <&can_clk>;
> > +			clock-names = "clkp1", "clkp2", "can_clk";
> >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> >  			resets = <&cpg 916>;
> >  			status = "disabled";
> > @@ -821,8 +823,10 @@
> >  				     "renesas,rcar-gen3-can";
> >  			reg = <0 0xe6c38000 0 0x1000>;
> >  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> > -			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> > -			clock-names = "clkp1", "can_clk";
> > +			clocks = <&cpg CPG_MOD 915>,
> > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > +				 <&can_clk>;
> > +			clock-names = "clkp1", "clkp2", "can_clk";
> >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> >  			resets = <&cpg 915>;
> >  			status = "disabled";
> > -- 
> > 2.7.4
> > 
> 

RE: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes

[Fabrizio Castro]

Hello Simon,

> From: Simon Horman <horms@verge.net.au>
> Sent: 28 January 2019 13:03
> Subject: Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes
> 
> On Thu, Jan 17, 2019 at 01:05:42PM +0100, Simon Horman wrote:
> > On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote:
> > > According to the latest information, clkp2 is available on RZ/G2.
> > > Modify CAN0 and CAN1 nodes accordingly.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> >
> > Taking your word for the motivation for this change,
> > this patch seems fine to me but I would like to wait for review
> > from others.
> >
> > Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> 
> I am marking this as deferred until R8A774C0_CLK_CANFD
> shows up in an rc release.
> 
> Alternatively I'd be happy to take a version that uses
> numeric values, followed up by a patch to switching to R8A774C0_CLK_CANFD
> once it is available in an rc release.
> 
> Please repost or otherwise ping me as appropriate.

It seems like this patch still applies without conflicts, do you mind taking it now
as R8A774C0_CLK_CANFD is finally available?

Thanks,
Fab

> 
> >
> > > ---
> > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
> > >  1 file changed, 8 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > index 3970aaf..326ab3a 100644
> > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > @@ -809,8 +809,10 @@
> > >  				     "renesas,rcar-gen3-can";
> > >  			reg = <0 0xe6c30000 0 0x1000>;
> > >  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> > > -			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> > > -			clock-names = "clkp1", "can_clk";
> > > +			clocks = <&cpg CPG_MOD 916>,
> > > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > > +				 <&can_clk>;
> > > +			clock-names = "clkp1", "clkp2", "can_clk";
> > >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > >  			resets = <&cpg 916>;
> > >  			status = "disabled";
> > > @@ -821,8 +823,10 @@
> > >  				     "renesas,rcar-gen3-can";
> > >  			reg = <0 0xe6c38000 0 0x1000>;
> > >  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> > > -			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> > > -			clock-names = "clkp1", "can_clk";
> > > +			clocks = <&cpg CPG_MOD 915>,
> > > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > > +				 <&can_clk>;
> > > +			clock-names = "clkp1", "clkp2", "can_clk";
> > >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > >  			resets = <&cpg 915>;
> > >  			status = "disabled";
> > > --
> > > 2.7.4
> > >
> >

Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes

[Simon Horman]

On Tue, Mar 19, 2019 at 11:12:33AM +0000, Fabrizio Castro wrote:
> Hello Simon,
> 
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 28 January 2019 13:03
> > Subject: Re: [PATCH 10/11] arm64: dts: renesas: r8a774c0: Add clkp2 clock to CAN nodes
> > 
> > On Thu, Jan 17, 2019 at 01:05:42PM +0100, Simon Horman wrote:
> > > On Wed, Jan 16, 2019 at 06:37:53PM +0000, Fabrizio Castro wrote:
> > > > According to the latest information, clkp2 is available on RZ/G2.
> > > > Modify CAN0 and CAN1 nodes accordingly.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> > >
> > > Taking your word for the motivation for this change,
> > > this patch seems fine to me but I would like to wait for review
> > > from others.
> > >
> > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> > 
> > I am marking this as deferred until R8A774C0_CLK_CANFD
> > shows up in an rc release.
> > 
> > Alternatively I'd be happy to take a version that uses
> > numeric values, followed up by a patch to switching to R8A774C0_CLK_CANFD
> > once it is available in an rc release.
> > 
> > Please repost or otherwise ping me as appropriate.
> 
> It seems like this patch still applies without conflicts, do you mind taking it now
> as R8A774C0_CLK_CANFD is finally available?

Thanks, I agree this should be ready now.
I've applied it for v5.2.

> 
> Thanks,
> Fab
> 
> > 
> > >
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 12 ++++++++----
> > > >  1 file changed, 8 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > index 3970aaf..326ab3a 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
> > > > @@ -809,8 +809,10 @@
> > > >  				     "renesas,rcar-gen3-can";
> > > >  			reg = <0 0xe6c30000 0 0x1000>;
> > > >  			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> > > > -			clocks = <&cpg CPG_MOD 916>, <&can_clk>;
> > > > -			clock-names = "clkp1", "can_clk";
> > > > +			clocks = <&cpg CPG_MOD 916>,
> > > > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > > > +				 <&can_clk>;
> > > > +			clock-names = "clkp1", "clkp2", "can_clk";
> > > >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > >  			resets = <&cpg 916>;
> > > >  			status = "disabled";
> > > > @@ -821,8 +823,10 @@
> > > >  				     "renesas,rcar-gen3-can";
> > > >  			reg = <0 0xe6c38000 0 0x1000>;
> > > >  			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> > > > -			clocks = <&cpg CPG_MOD 915>, <&can_clk>;
> > > > -			clock-names = "clkp1", "can_clk";
> > > > +			clocks = <&cpg CPG_MOD 915>,
> > > > +				 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
> > > > +				 <&can_clk>;
> > > > +			clock-names = "clkp1", "clkp2", "can_clk";
> > > >  			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> > > >  			resets = <&cpg 915>;
> > > >  			status = "disabled";
> > > > --
> > > > 2.7.4
> > > >
> > >
> 

[PATCH 11/11] dt-bindings: can: rcar_canfd: document r8a774c0 support

[Fabrizio Castro]

Document the support for rcar_canfd on R8A774C0 SoC devices.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
This patch depends on:
https://patchwork.kernel.org/patch/10687999/
https://patchwork.kernel.org/patch/10688001/

 Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
index 41049fe..32f051f 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -3,7 +3,8 @@ Renesas R-Car CAN FD controller Device Tree Bindings
 
 Required properties:
 - compatible: Must contain one or more of the following:
-  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
+  - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
   - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
   - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
   - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
@@ -28,12 +29,13 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
 child node supports the "status" property only, which is used to
 enable/disable the respective channel.
 
-Required properties for "renesas,r8a7795-canfd", "renesas,r8a7796-canfd",
-"renesas,r8a77965-canfd" and "renesas,r8a77990-canfd" compatible:
-In R8A7795, R8A7796, R8A77965 and R8A77990 SoCs, canfd clock is a div6 clock
-and can be used by both CAN and CAN FD controller at the same time. It needs
-to be scaled to maximum frequency if any of these controllers use it. This is
-done using the below properties:
+Required properties for "renesas,r8a774c0-canfd", "renesas,r8a7795-canfd",
+"renesas,r8a7796-canfd", "renesas,r8a77965-canfd", and "renesas,r8a77990-canfd"
+compatible:
+In R8A774C0, R8A7795, R8A7796, R8A77965, and R8A77990 SoCs, canfd clock is a
+div6 clock and can be used by both CAN and CAN FD controller at the same time.
+It needs to be scaled to maximum frequency if any of these controllers use it.
+This is done using the below properties:
 
 - assigned-clocks: phandle of canfd clock.
 - assigned-clock-rates: maximum frequency of this clock.
-- 
2.7.4

Re: [PATCH 11/11] dt-bindings: can: rcar_canfd: document r8a774c0 support

[Simon Horman]

On Wed, Jan 16, 2019 at 06:37:54PM +0000, Fabrizio Castro wrote:
> Document the support for rcar_canfd on R8A774C0 SoC devices.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
> This patch depends on:
> https://patchwork.kernel.org/patch/10687999/
> https://patchwork.kernel.org/patch/10688001/
> 
>  Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 16 +++++++++-------

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> index 41049fe..32f051f 100644
> --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> @@ -3,7 +3,8 @@ Renesas R-Car CAN FD controller Device Tree Bindings
>  
>  Required properties:
>  - compatible: Must contain one or more of the following:
> -  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
> +  - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
> +  - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
>    - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
>    - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
>    - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
> @@ -28,12 +29,13 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
>  child node supports the "status" property only, which is used to
>  enable/disable the respective channel.
>  
> -Required properties for "renesas,r8a7795-canfd", "renesas,r8a7796-canfd",
> -"renesas,r8a77965-canfd" and "renesas,r8a77990-canfd" compatible:
> -In R8A7795, R8A7796, R8A77965 and R8A77990 SoCs, canfd clock is a div6 clock
> -and can be used by both CAN and CAN FD controller at the same time. It needs
> -to be scaled to maximum frequency if any of these controllers use it. This is
> -done using the below properties:
> +Required properties for "renesas,r8a774c0-canfd", "renesas,r8a7795-canfd",
> +"renesas,r8a7796-canfd", "renesas,r8a77965-canfd", and "renesas,r8a77990-canfd"
> +compatible:
> +In R8A774C0, R8A7795, R8A7796, R8A77965, and R8A77990 SoCs, canfd clock is a
> +div6 clock and can be used by both CAN and CAN FD controller at the same time.
> +It needs to be scaled to maximum frequency if any of these controllers use it.
> +This is done using the below properties:
>  
>  - assigned-clocks: phandle of canfd clock.
>  - assigned-clock-rates: maximum frequency of this clock.
> -- 
> 2.7.4
> 

Re: [PATCH 11/11] dt-bindings: can: rcar_canfd: document r8a774c0 support

[Rob Herring]

On Wed, 16 Jan 2019 18:37:54 +0000, Fabrizio Castro wrote:
> Document the support for rcar_canfd on R8A774C0 SoC devices.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
> This patch depends on:
> https://patchwork.kernel.org/patch/10687999/
> https://patchwork.kernel.org/patch/10688001/
> 
>  Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH 11/11] dt-bindings: can: rcar_canfd: document r8a774c0 support

[Fabrizio Castro]

Hello Marc,

I am sorry to bother you.
Do you think you can take this patch?

Thanks,
Fab

> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Sent: 16 January 2019 18:38
> Subject: [PATCH 11/11] dt-bindings: can: rcar_canfd: document r8a774c0 support
> 
> Document the support for rcar_canfd on R8A774C0 SoC devices.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
> ---
> This patch depends on:
> https://patchwork.kernel.org/patch/10687999/
> https://patchwork.kernel.org/patch/10688001/
> 
>  Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> index 41049fe..32f051f 100644
> --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> @@ -3,7 +3,8 @@ Renesas R-Car CAN FD controller Device Tree Bindings
> 
>  Required properties:
>  - compatible: Must contain one or more of the following:
> -  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
> +  - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
> +  - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
>    - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
>    - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
>    - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
> @@ -28,12 +29,13 @@ The name of the child nodes are "channel0" and "channel1" respectively. Each
>  child node supports the "status" property only, which is used to
>  enable/disable the respective channel.
> 
> -Required properties for "renesas,r8a7795-canfd", "renesas,r8a7796-canfd",
> -"renesas,r8a77965-canfd" and "renesas,r8a77990-canfd" compatible:
> -In R8A7795, R8A7796, R8A77965 and R8A77990 SoCs, canfd clock is a div6 clock
> -and can be used by both CAN and CAN FD controller at the same time. It needs
> -to be scaled to maximum frequency if any of these controllers use it. This is
> -done using the below properties:
> +Required properties for "renesas,r8a774c0-canfd", "renesas,r8a7795-canfd",
> +"renesas,r8a7796-canfd", "renesas,r8a77965-canfd", and "renesas,r8a77990-canfd"
> +compatible:
> +In R8A774C0, R8A7795, R8A7796, R8A77965, and R8A77990 SoCs, canfd clock is a
> +div6 clock and can be used by both CAN and CAN FD controller at the same time.
> +It needs to be scaled to maximum frequency if any of these controllers use it.
> +This is done using the below properties:
> 
>  - assigned-clocks: phandle of canfd clock.
>  - assigned-clock-rates: maximum frequency of this clock.
> --
> 2.7.4