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* [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches
@ 2019-05-02 12:32 Geert Uytterhoeven
  2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
                   ` (4 more replies)
  0 siblings, 5 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

	Hi all,

Unlike on most other Renesas SoCs, the GPIO controller block on RZ/A1
and RZ/A2 SoCs lack interrupt functionality.  While the GPIOs can be
routed to the GIC as pin interrupts, this is of limited use, as the
PL390 or GIC-400 supports rising edge and high-level interrupts only.

Fortunately RZ/A1 and RZ/A2 SoCs contain a small front-end for the GIC,
allowing to use up to 8 external interrupts, with configurable sense
select.

Hence this patch series adds DT bindings and a driver for this
front-end, adds a device node for it in the RZ/A1H DTS, and uses it to
enable support for the 3 input switches on the Renesas RSK+RZA1
development board.

Changes compared to v2:
  - Add Tested-by,
  - Use standard interrupt-map instead of custom renesas,gic-spi-base.
    I'm still a bit puzzled by the confusing semantics (double meaning)
    of child and parent unit addresses in interrupt-map.

Changes compared to v1:
  - Add Reviewed-by,
  - Replace gic_spi_base in OF match data by renesas,gic-spi-base in DT,
  - Document RZ/A2M,
  - Use u16 for register values,
  - Use relaxed I/O accessors,
  - Use "rza1-irqc" as irq_chip class name,
  - Enable driver on RZ/A2M.

Dependencies:
  - Patch 3 depends on patch 2,
  - Patch 4 can be applied as soon as the DT bindings in patch 1 have
    been accepted,
  - Patch 5 depends on patch 4.

Upstream strategy:
  - Patches 1-2 are intended to be applied to the irqchip tree,
  - Patches 3-5 are meant for the Renesas tree.

This has been tested on RSK+RZA1 with evtest and s2ram wake-up.
I have verified proper operation of low-level and rising/falling sense
select, too.

Thanks!

Geert Uytterhoeven (5):
  dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt
    Controller
  irqchip: Add Renesas RZ/A1 Interrupt Controller driver
  soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
  ARM: dts: r7s72100: Add IRQC device node
  ARM: dts: rskrza1: Add input switches

 .../renesas,rza1-irqc.txt                     |  43 +++
 arch/arm/boot/dts/r7s72100-rskrza1.dts        |  38 +++
 arch/arm/boot/dts/r7s72100.dtsi               |  19 ++
 drivers/irqchip/Kconfig                       |   4 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-renesas-rza1.c            | 283 ++++++++++++++++++
 drivers/soc/renesas/Kconfig                   |   4 +-
 7 files changed, 391 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
 create mode 100644 drivers/irqchip/irq-renesas-rza1.c

-- 
2.17.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller
  2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
@ 2019-05-02 12:32 ` Geert Uytterhoeven
  2019-05-07 13:51   ` Simon Horman
  2019-05-13 17:20   ` Rob Herring
  2019-05-02 12:32 ` [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
                   ` (3 subsequent siblings)
  4 siblings, 2 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

Add DT bindings for the Renesas RZ/A1 Interrupt Controller.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
    of renesas,gic-spi-base,

v2:
  - Add "renesas,gic-spi-base",
  - Document RZ/A2M.
---
 .../renesas,rza1-irqc.txt                     | 43 +++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
new file mode 100644
index 0000000000000000..727b7e4cd6e01110
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
@@ -0,0 +1,43 @@
+DT bindings for the Renesas RZ/A1 Interrupt Controller
+
+The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
+RZ/A1 and RZ/A2 SoCs:
+  - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
+    interrupts,
+  - NMI edge select.
+
+Required properties:
+  - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
+		fallback.
+		Examples with soctypes are:
+		  - "renesas,r7s72100-irqc" (RZ/A1H)
+		  - "renesas,r7s9210-irqc" (RZ/A2M)
+  - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
+				 in interrupts.txt in this directory)
+  - #address-cells: Must be zero
+  - interrupt-controller: Marks the device as an interrupt controller
+  - reg: Base address and length of the memory resource used by the interrupt
+         controller
+  - interrupt-map: Specifies the mapping from external interrupts to GIC
+		   interrupts
+  - interrupt-map-mask: Must be <7 0>
+
+Example:
+
+	irqc: interrupt-controller@fcfef800 {
+		compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+		#interrupt-cells = <2>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0xfcfef800 0x6>;
+		interrupt-map =
+			<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map-mask = <7 0>;
+	};
-- 
2.17.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver
  2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
  2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
@ 2019-05-02 12:32 ` Geert Uytterhoeven
  2019-05-07 13:53   ` Simon Horman
  2019-05-02 12:32 ` [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M Geert Uytterhoeven
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

Add a driver for the Renesas RZ/A1 Interrupt Controller.

This supports using up to 8 external interrupts on RZ/A1, with
configurable sense select.

NMI edge select is not yet supported.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Chris Brandt <chris.brandt@renesas.com>
---
For simplicity, interrupt-map-mask is not parsed, but ignored.

I also considered extracting the parsing code in of_irq_parse_raw() in a
new public helper function:

    int of_irq_parse_map(struct device_node **ipar, u32 *addrsize,
			 u32 *intsize, const __be32 **match_array,
			 struct of_phandle_args *out_irq);

However, that API is a bit ugly due to many output parameters
(of_irq_parse_raw() needs to iterate the interrupt hierarchy).
In addition, it's less efficient for irq-renesas-rza1.c, as the
interrupt-map must be parsed 8 times.

v3:
  - Add Tested-by,
  - Replace renesas,gic-spi-base in DT by interrupt-map in DT,

v2:
  - Use u16 for register values,
  - Use relaxed I/O accessors,
  - Use "rza1-irqc" as irq_chip class name,
  - Replace gic_spi_base in OF match data by renesas,gic-spi-base in DT.
---
 drivers/irqchip/Kconfig            |   4 +
 drivers/irqchip/Makefile           |   1 +
 drivers/irqchip/irq-renesas-rza1.c | 283 +++++++++++++++++++++++++++++
 3 files changed, 288 insertions(+)
 create mode 100644 drivers/irqchip/irq-renesas-rza1.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 8c1c67f9a4bb5bf6..db07db4c48486649 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -224,6 +224,10 @@ config RENESAS_IRQC
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 
+config RENESAS_RZA1_IRQC
+	bool
+	select IRQ_DOMAIN_HIERARCHY
+
 config ST_IRQCHIP
 	bool
 	select REGMAP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f8c66e958a64deaa..ce37fba74effad8c 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_JCORE_AIC)			+= irq-jcore-aic.o
 obj-$(CONFIG_RDA_INTC)			+= irq-rda-intc.o
 obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
 obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
+obj-$(CONFIG_RENESAS_RZA1_IRQC)		+= irq-renesas-rza1.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
 obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
 obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
diff --git a/drivers/irqchip/irq-renesas-rza1.c b/drivers/irqchip/irq-renesas-rza1.c
new file mode 100644
index 0000000000000000..b1f19b210190184f
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-rza1.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/A1 IRQC Driver
+ *
+ * Copyright (C) 2019 Glider bvba
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define IRQC_NUM_IRQ		8
+
+#define ICR0			0	/* Interrupt Control Register 0 */
+
+#define ICR0_NMIL		BIT(15)	/* NMI Input Level (0=low, 1=high) */
+#define ICR0_NMIE		BIT(8)	/* Edge Select (0=falling, 1=rising) */
+#define ICR0_NMIF		BIT(1)	/* NMI Interrupt Request */
+
+#define ICR1			2	/* Interrupt Control Register 1 */
+
+#define ICR1_IRQS(n, sense)	((sense) << ((n) * 2))	/* IRQ Sense Select */
+#define ICR1_IRQS_LEVEL_LOW	0
+#define ICR1_IRQS_EDGE_FALLING	1
+#define ICR1_IRQS_EDGE_RISING	2
+#define ICR1_IRQS_EDGE_BOTH	3
+#define ICR1_IRQS_MASK(n)	ICR1_IRQS((n), 3)
+
+#define IRQRR			4	/* IRQ Interrupt Request Register */
+
+
+struct rza1_irqc_priv {
+	struct device *dev;
+	void __iomem *base;
+	struct irq_chip chip;
+	struct irq_domain *irq_domain;
+	struct of_phandle_args map[IRQC_NUM_IRQ];
+};
+
+static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data)
+{
+	return data->domain->host_data;
+}
+
+static void rza1_irqc_eoi(struct irq_data *d)
+{
+	struct rza1_irqc_priv *priv = irq_data_to_priv(d);
+	u16 bit = BIT(irqd_to_hwirq(d));
+	u16 tmp;
+
+	tmp = readw_relaxed(priv->base + IRQRR);
+	if (tmp & bit)
+		writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
+			       priv->base + IRQRR);
+
+	irq_chip_eoi_parent(d);
+}
+
+static int rza1_irqc_set_type(struct irq_data *d, unsigned int type)
+{
+	struct rza1_irqc_priv *priv = irq_data_to_priv(d);
+	unsigned int hw_irq = irqd_to_hwirq(d);
+	u16 sense, tmp;
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_LEVEL_LOW:
+		sense = ICR1_IRQS_LEVEL_LOW;
+		break;
+
+	case IRQ_TYPE_EDGE_FALLING:
+		sense = ICR1_IRQS_EDGE_FALLING;
+		break;
+
+	case IRQ_TYPE_EDGE_RISING:
+		sense = ICR1_IRQS_EDGE_RISING;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		sense = ICR1_IRQS_EDGE_BOTH;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	tmp = readw_relaxed(priv->base + ICR1);
+	tmp &= ~ICR1_IRQS_MASK(hw_irq);
+	tmp |= ICR1_IRQS(hw_irq, sense);
+	writew_relaxed(tmp, priv->base + ICR1);
+	return 0;
+}
+
+static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq,
+			   unsigned int nr_irqs, void *arg)
+{
+	struct rza1_irqc_priv *priv = domain->host_data;
+	struct irq_fwspec *fwspec = arg;
+	unsigned int hwirq = fwspec->param[0];
+	struct irq_fwspec spec;
+	unsigned int i;
+	int ret;
+
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
+					    priv);
+	if (ret)
+		return ret;
+
+	spec.fwnode = &priv->dev->of_node->fwnode;
+	spec.param_count = priv->map[hwirq].args_count;
+	for (i = 0; i < spec.param_count; i++)
+		spec.param[i] = priv->map[hwirq].args[i];
+
+	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec);
+}
+
+static int rza1_irqc_translate(struct irq_domain *domain,
+			       struct irq_fwspec *fwspec, unsigned long *hwirq,
+			       unsigned int *type)
+{
+	if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)
+		return -EINVAL;
+
+	*hwirq = fwspec->param[0];
+	*type = fwspec->param[1];
+	return 0;
+}
+
+static const struct irq_domain_ops rza1_irqc_domain_ops = {
+	.alloc = rza1_irqc_alloc,
+	.translate = rza1_irqc_translate,
+};
+
+static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv,
+			       struct device_node *gic_node)
+{
+	unsigned int imaplen, i, j, ret;
+	struct device *dev = priv->dev;
+	struct device_node *ipar;
+	const __be32 *imap;
+	u32 intsize;
+
+	imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);
+	if (!imap)
+		return -EINVAL;
+
+	for (i = 0; i < IRQC_NUM_IRQ; i++) {
+		if (imaplen < 3)
+			return -EINVAL;
+
+		/* Check interrupt number, ignore sense */
+		if (be32_to_cpup(imap) != i)
+			return -EINVAL;
+
+		ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2));
+		if (ipar != gic_node) {
+			of_node_put(ipar);
+			return -EINVAL;
+		}
+
+		imap += 3;
+		imaplen -= 3;
+
+		ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
+		of_node_put(ipar);
+		if (ret)
+			return ret;
+
+		if (imaplen < intsize)
+			return -EINVAL;
+
+		priv->map[i].args_count = intsize;
+		for (j = 0; j < intsize; j++)
+			priv->map[i].args[j] = be32_to_cpup(imap++);
+
+		imaplen -= intsize;
+	}
+
+	return 0;
+}
+
+static int rza1_irqc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct irq_domain *parent = NULL;
+	struct device_node *gic_node;
+	struct rza1_irqc_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, priv);
+	priv->dev = dev;
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	gic_node = of_irq_find_parent(np);
+	if (gic_node) {
+		parent = irq_find_host(gic_node);
+		of_node_put(gic_node);
+	}
+
+	if (!parent) {
+		dev_err(dev, "cannot find parent domain\n");
+		return -ENODEV;
+	}
+
+	ret = rza1_irqc_parse_map(priv, gic_node);
+	if (ret) {
+		dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);
+		return ret;
+	}
+
+	priv->chip.name = "rza1-irqc",
+	priv->chip.irq_mask = irq_chip_mask_parent,
+	priv->chip.irq_unmask = irq_chip_unmask_parent,
+	priv->chip.irq_eoi = rza1_irqc_eoi,
+	priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy,
+	priv->chip.irq_set_type = rza1_irqc_set_type,
+	priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
+
+	priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
+						    np, &rza1_irqc_domain_ops,
+						    priv);
+	if (!priv->irq_domain) {
+		dev_err(dev, "cannot initialize irq domain\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int rza1_irqc_remove(struct platform_device *pdev)
+{
+	struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
+
+	irq_domain_remove(priv->irq_domain);
+	return 0;
+}
+
+static const struct of_device_id rza1_irqc_dt_ids[] = {
+	{ .compatible = "renesas,rza1-irqc" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
+
+static struct platform_driver rza1_irqc_device_driver = {
+	.probe		= rza1_irqc_probe,
+	.remove		= rza1_irqc_remove,
+	.driver		= {
+		.name	= "renesas_rza1_irqc",
+		.of_match_table	= rza1_irqc_dt_ids,
+	}
+};
+
+static int __init rza1_irqc_init(void)
+{
+	return platform_driver_register(&rza1_irqc_device_driver);
+}
+postcore_initcall(rza1_irqc_init);
+
+static void __exit rza1_irqc_exit(void)
+{
+	platform_driver_unregister(&rza1_irqc_device_driver);
+}
+module_exit(rza1_irqc_exit);
+
+MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
+MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.17.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
  2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
  2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
  2019-05-02 12:32 ` [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
@ 2019-05-02 12:32 ` Geert Uytterhoeven
  2019-06-06  8:37   ` Simon Horman
  2019-05-02 12:32 ` [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node Geert Uytterhoeven
  2019-05-02 12:32 ` [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
  4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

Auto-enable support for the RZ/A1 Interrupt Controller when configuring
a kernel which supports RZ/A1H or RZ/A2M SoCs.
Keep selects sorted while at it.

This is similar to how interrupt controllers for other Renesas SoCs are
enabled.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
v3:
  - No changes,

v2:
  - Add Reviewed-by,
  - Add RZ/A2M,
  - Sort RZ/A1H selects.
---
 drivers/soc/renesas/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 68bfca6f20ddf8a7..2bbf49e5d441808b 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -57,14 +57,16 @@ config ARCH_R7S72100
 	bool "RZ/A1H (R7S72100)"
 	select PM
 	select PM_GENERIC_DOMAINS
-	select SYS_SUPPORTS_SH_MTU2
 	select RENESAS_OSTM
+	select RENESAS_RZA1_IRQC
+	select SYS_SUPPORTS_SH_MTU2
 
 config ARCH_R7S9210
 	bool "RZ/A2 (R7S9210)"
 	select PM
 	select PM_GENERIC_DOMAINS
 	select RENESAS_OSTM
+	select RENESAS_RZA1_IRQC
 
 config ARCH_R8A73A4
 	bool "R-Mobile APE6 (R8A73A40)"
-- 
2.17.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node
  2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
                   ` (2 preceding siblings ...)
  2019-05-02 12:32 ` [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M Geert Uytterhoeven
@ 2019-05-02 12:32 ` Geert Uytterhoeven
  2019-05-20 11:27   ` Simon Horman
  2019-05-02 12:32 ` [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
  4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC.  This allows to use up to 8 external interrupts with configurable
sense select.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
v3:
  - Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
    of renesas,gic-spi-base,

v2:
  - Add Reviewed-by,
  - Add "renesas,gic-spi-base".
---
 arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 2211f88ede2ad351..d03dcd919d6f5cfb 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -670,6 +670,25 @@
 			status = "disabled";
 		};
 
+		irqc: interrupt-controller@fcfef800 {
+			compatible = "renesas,r7s72100-irqc",
+				     "renesas,rza1-irqc";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0xfcfef800 0x6>;
+			interrupt-map =
+				<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-map-mask = <7 0>;
+		};
+
 		mtu2: timer@fcff0000 {
 			compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 			reg = <0xfcff0000 0x400>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches
  2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
                   ` (3 preceding siblings ...)
  2019-05-02 12:32 ` [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node Geert Uytterhoeven
@ 2019-05-02 12:32 ` Geert Uytterhoeven
  2019-05-20 11:29   ` Simon Horman
  4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-05-02 12:32 UTC (permalink / raw)
  To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Simon Horman, Magnus Damm, Chris Brandt
  Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven

Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
development board.

Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
does not include interrupt support.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes,

v1:
  - Use rza1-irqc instead of gic.

v0:
  - Sent as an RFC in a reply to another thread.
---
 arch/arm/boot/dts/r7s72100-rskrza1.dts | 38 ++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index ff24301dc1be54de..99acfe4fe11aaed9 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 #include "r7s72100.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
 
 / {
@@ -28,6 +29,37 @@
 		reg = <0x08000000 0x02000000>;
 	};
 
+	keyboard {
+		compatible = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&keyboard_pins>;
+
+		key-1 {
+			interrupt-parent = <&irqc>;
+			interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_1>;
+			label = "SW1";
+			wakeup-source;
+		};
+
+		key-2 {
+			interrupt-parent = <&irqc>;
+			interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_2>;
+			label = "SW2";
+			wakeup-source;
+		};
+
+		key-3 {
+			interrupt-parent = <&irqc>;
+			interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
+			linux,code = <KEY_3>;
+			label = "SW3";
+			wakeup-source;
+		};
+	};
+
 	lbsc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -101,6 +133,12 @@
 			 <RZA1_PINMUX(1, 7, 1)>;	/* RIIC3SDA */
 	};
 
+	keyboard_pins: keyboard {
+		pinmux = <RZA1_PINMUX(1, 9, 3)>,	/* IRQ3 */
+			 <RZA1_PINMUX(1, 8, 3)>,	/* IRQ2 */
+			 <RZA1_PINMUX(1, 11, 3)>;	/* IRQ5 */
+	};
+
 	/* Serial Console */
 	scif2_pins: serial2 {
 		pinmux = <RZA1_PINMUX(3, 0, 6)>,	/* TxD2 */
-- 
2.17.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller
  2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
@ 2019-05-07 13:51   ` Simon Horman
  2019-05-13 12:17     ` Simon Horman
  2019-05-13 17:20   ` Rob Herring
  1 sibling, 1 reply; 13+ messages in thread
From: Simon Horman @ 2019-05-07 13:51 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Thu, May 02, 2019 at 02:32:16PM +0200, Geert Uytterhoeven wrote:
> Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver
  2019-05-02 12:32 ` [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
@ 2019-05-07 13:53   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-05-07 13:53 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Thu, May 02, 2019 at 02:32:17PM +0200, Geert Uytterhoeven wrote:
> Add a driver for the Renesas RZ/A1 Interrupt Controller.
> 
> This supports using up to 8 external interrupts on RZ/A1, with
> configurable sense select.
> 
> NMI edge select is not yet supported.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Tested-by: Chris Brandt <chris.brandt@renesas.com>

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>


^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller
  2019-05-07 13:51   ` Simon Horman
@ 2019-05-13 12:17     ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-05-13 12:17 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Tue, May 07, 2019 at 03:51:44PM +0200, Simon Horman wrote:
> On Thu, May 02, 2019 at 02:32:16PM +0200, Geert Uytterhoeven wrote:
> > Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
> > 
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

FWIIW, Acceptance/Approval of this patch is blocking me
applying the soc and dt patches of this series.

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller
  2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
  2019-05-07 13:51   ` Simon Horman
@ 2019-05-13 17:20   ` Rob Herring
  1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2019-05-13 17:20 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Mark Rutland,
	Simon Horman, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel, Geert Uytterhoeven

On Thu,  2 May 2019 14:32:16 +0200, Geert Uytterhoeven wrote:
> Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
>   - Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
>     of renesas,gic-spi-base,
> 
> v2:
>   - Add "renesas,gic-spi-base",
>   - Document RZ/A2M.
> ---
>  .../renesas,rza1-irqc.txt                     | 43 +++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node
  2019-05-02 12:32 ` [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node Geert Uytterhoeven
@ 2019-05-20 11:27   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-05-20 11:27 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Thu, May 02, 2019 at 02:32:19PM +0200, Geert Uytterhoeven wrote:
> Enable support for the IRQC on RZ/A1H, which is a small front-end to the
> GIC.  This allows to use up to 8 external interrupts with configurable
> sense select.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Thanks Geert,

I have applied this for inclusion in v5.3

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches
  2019-05-02 12:32 ` [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
@ 2019-05-20 11:29   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-05-20 11:29 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Thu, May 02, 2019 at 02:32:20PM +0200, Geert Uytterhoeven wrote:
> Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
> development board.
> 
> Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
> does not include interrupt support.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks Geert,

I have applied this for inclusion in v5.3

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M
  2019-05-02 12:32 ` [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M Geert Uytterhoeven
@ 2019-06-06  8:37   ` Simon Horman
  0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-06-06  8:37 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
	Mark Rutland, Magnus Damm, Chris Brandt, devicetree,
	linux-renesas-soc, linux-kernel

On Thu, May 02, 2019 at 02:32:18PM +0200, Geert Uytterhoeven wrote:
> Auto-enable support for the RZ/A1 Interrupt Controller when configuring
> a kernel which supports RZ/A1H or RZ/A2M SoCs.
> Keep selects sorted while at it.
> 
> This is similar to how interrupt controllers for other Renesas SoCs are
> enabled.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Thanks, applied for v5.3.

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, back to index

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
2019-05-07 13:51   ` Simon Horman
2019-05-13 12:17     ` Simon Horman
2019-05-13 17:20   ` Rob Herring
2019-05-02 12:32 ` [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
2019-05-07 13:53   ` Simon Horman
2019-05-02 12:32 ` [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M Geert Uytterhoeven
2019-06-06  8:37   ` Simon Horman
2019-05-02 12:32 ` [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node Geert Uytterhoeven
2019-05-20 11:27   ` Simon Horman
2019-05-02 12:32 ` [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
2019-05-20 11:29   ` Simon Horman

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