From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: [PATCH v3 2/6] pinctrl: renesas: add I/O voltage level flag
Date: Tue, 12 Jan 2021 17:59:08 +0100 [thread overview]
Message-ID: <20210112165912.30876-3-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20210112165912.30876-1-uli+renesas@fpond.eu>
This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/pinctrl/renesas/pinctrl.c | 16 ++++++++++++++--
drivers/pinctrl/renesas/sh_pfc.h | 9 +++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index ac542d278a38..f0f2b393a554 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -634,6 +634,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -648,7 +651,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
val = sh_pfc_read(pfc, pocctrl);
spin_unlock_irqrestore(&pfc->lock, flags);
- arg = (val & BIT(bit)) ? 3300 : 1800;
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ arg = (val & BIT(bit)) ? 3300 : lower_voltage;
break;
}
@@ -702,6 +708,9 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
case PIN_CONFIG_POWER_SOURCE: {
unsigned int mV = pinconf_to_config_argument(configs[i]);
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -712,7 +721,10 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
- if (mV != 1800 && mV != 3300)
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ if (mV != lower_voltage && mV != 3300)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 1404bd897d25..9787dc893a33 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -31,6 +31,15 @@ enum {
SH_PFC_PIN_CFG_PULL_DOWN)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
+
+#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
+#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
+
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_18_33)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_25_33)
+
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {
--
2.20.1
next prev parent reply other threads:[~2021-01-12 17:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 16:59 [PATCH v3 0/6] pinctrl: renesas: basic R8A779A0 (V3U) support Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 1/6] pinctrl: renesas: implement unlock register masks Ulrich Hecht
2021-01-13 13:25 ` Geert Uytterhoeven
2021-01-12 16:59 ` Ulrich Hecht [this message]
2021-01-13 13:29 ` [PATCH v3 2/6] pinctrl: renesas: add I/O voltage level flag Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 3/6] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Ulrich Hecht
2021-01-13 13:32 ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 5/6] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 6/6] dt-bindings: pinctrl: sh-pfc: Document r8a779a0 PFC support Ulrich Hecht
2021-01-13 13:43 ` Geert Uytterhoeven
[not found] ` <20210112165912.30876-5-uli+renesas@fpond.eu>
2021-01-13 13:37 ` [PATCH v3 4/6] pinctrl: renesas: Initial R8A779A0 (V3U) " Geert Uytterhoeven
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