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From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>,
	Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: [PATCH v3 3/6] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros
Date: Tue, 12 Jan 2021 17:59:09 +0100	[thread overview]
Message-ID: <20210112165912.30876-4-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20210112165912.30876-1-uli+renesas@fpond.eu>

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/pinctrl/renesas/sh_pfc.h | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 9787dc893a33..4367fe5b0f4a 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -460,9 +460,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
 	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
 #define PORT_GP_1(bank, pin, fn, sfx)	PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
 
-#define PORT_GP_CFG_4(bank, fn, sfx, cfg)				\
+#define PORT_GP_CFG_2(bank, fn, sfx, cfg)				\
 	PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),				\
+	PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg)
+#define PORT_GP_2(bank, fn, sfx)	PORT_GP_CFG_2(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_4(bank, fn, sfx, cfg)				\
+	PORT_GP_CFG_2(bank, fn, sfx, cfg)				\
 	PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),				\
 	PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 #define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)
@@ -581,9 +585,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
 	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
 #define PORT_GP_30(bank, fn, sfx)	PORT_GP_CFG_30(bank, fn, sfx, 0)
 
-#define PORT_GP_CFG_32(bank, fn, sfx, cfg)				\
+#define PORT_GP_CFG_31(bank, fn, sfx, cfg)				\
 	PORT_GP_CFG_30(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg),				\
+	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
+#define PORT_GP_31(bank, fn, sfx)	PORT_GP_CFG_31(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_32(bank, fn, sfx, cfg)				\
+	PORT_GP_CFG_31(bank, fn, sfx, cfg),				\
 	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
 #define PORT_GP_32(bank, fn, sfx)	PORT_GP_CFG_32(bank, fn, sfx, 0)
 
-- 
2.20.1


  parent reply	other threads:[~2021-01-12 17:02 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 16:59 [PATCH v3 0/6] pinctrl: renesas: basic R8A779A0 (V3U) support Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 1/6] pinctrl: renesas: implement unlock register masks Ulrich Hecht
2021-01-13 13:25   ` Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 2/6] pinctrl: renesas: add I/O voltage level flag Ulrich Hecht
2021-01-13 13:29   ` Geert Uytterhoeven
2021-01-12 16:59 ` Ulrich Hecht [this message]
2021-01-13 13:32   ` [PATCH v3 3/6] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Geert Uytterhoeven
2021-01-12 16:59 ` [PATCH v3 5/6] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2021-01-12 16:59 ` [PATCH v3 6/6] dt-bindings: pinctrl: sh-pfc: Document r8a779a0 PFC support Ulrich Hecht
2021-01-13 13:43   ` Geert Uytterhoeven
     [not found] ` <20210112165912.30876-5-uli+renesas@fpond.eu>
2021-01-13 13:37   ` [PATCH v3 4/6] pinctrl: renesas: Initial R8A779A0 (V3U) " Geert Uytterhoeven

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