* [PATCH v5 01/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 02/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
` (10 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Rob Herring
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe host module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/rcar-gen4-pci-host.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
new file mode 100644
index 000000000000..8ac4c2041a81
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Host
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie # R-Car Gen4
+
+ interrupts:
+ maxItems: 7
+
+ interrupt-names:
+ items:
+ - const: others
+ - const: dma
+ - const: correctable
+ - const: fatal
+ - const: nonfatal
+ - const: lp
+ - const: vndmsg
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "atu", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0 0xfe000000 0 0x00010000
+ 0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable", "fatal",
+ "nonfatal", "lp", "vndmsg";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <2>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 02/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 01/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
` (9 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Rob Herring
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe endpoint module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/rcar-gen4-pci-ep.yaml | 99 +++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
new file mode 100644
index 000000000000..3850e7038620
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Endpoint
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: atu
+ - const: appl
+ - const: addr_space
+
+ interrupts:
+ maxItems: 7
+
+ interrupt-names:
+ items:
+ - const: others
+ - const: dma
+ - const: correctable
+ - const: fatal
+ - const: nonfatal
+ - const: lp
+ - const: vndmsg
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ max-link-speed: true
+
+ num-lanes: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - resets
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d1000 0 0x1000>,
+ <0 0xe65d3000 0 0x2000>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "atu", "appl", "addr_space";
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable", "fatal",
+ "nonfatal", "lp", "vndmsg";
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ max-link-speed = <2>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 01/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 02/12] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-20 20:08 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
` (8 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add macros defining Maximum Link Width bits in Link Capabilities
Register.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
include/uapi/linux/pci_regs.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 57b8e2ffb1dd..c9f4c452e210 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -538,6 +538,13 @@
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
+#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
+#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
+#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
+#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
+#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
+#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
+#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
2022-09-05 7:12 ` [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
@ 2022-09-20 20:08 ` Bjorn Helgaas
2022-09-21 0:05 ` Yoshihiro Shimoda
0 siblings, 1 reply; 22+ messages in thread
From: Bjorn Helgaas @ 2022-09-20 20:08 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote:
> Add macros defining Maximum Link Width bits in Link Capabilities
> Register.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> include/uapi/linux/pci_regs.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 57b8e2ffb1dd..c9f4c452e210 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -538,6 +538,13 @@
> #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
> #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
> #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
> +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
> +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
> +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
> +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
> +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
> +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
In PCIe r6.0, x32 is mentioned a few times, but not actually defined
for Link Capabilities. Has it been defined in an ECN or something?
Bjorn
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
2022-09-20 20:08 ` Bjorn Helgaas
@ 2022-09-21 0:05 ` Yoshihiro Shimoda
2022-09-21 2:22 ` Bjorn Helgaas
0 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-21 0:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
Hi Bjorn,
Thank you for your review!
> From: Bjorn Helgaas, Sent: Wednesday, September 21, 2022 5:08 AM
>
> On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote:
> > Add macros defining Maximum Link Width bits in Link Capabilities
> > Register.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > include/uapi/linux/pci_regs.h | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index 57b8e2ffb1dd..c9f4c452e210 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -538,6 +538,13 @@
> > #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
> > #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
> > #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> > +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
> > +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
> > +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
> > +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
> > +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
> > +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
> > +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
>
> In PCIe r6.0, x32 is mentioned a few times, but not actually defined
> for Link Capabilities. Has it been defined in an ECN or something?
I should have looked PCIe r6.0, but I looked PCIe r4.0 v1.0 and it mentioned x32.
So, I wrote the x32 macro.
I'll drop PCI_EXP_LNKCAP_MLW_X32 on v6 patch.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
2022-09-21 0:05 ` Yoshihiro Shimoda
@ 2022-09-21 2:22 ` Bjorn Helgaas
2022-09-21 8:50 ` Yoshihiro Shimoda
0 siblings, 1 reply; 22+ messages in thread
From: Bjorn Helgaas @ 2022-09-21 2:22 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
On Wed, Sep 21, 2022 at 12:05:26AM +0000, Yoshihiro Shimoda wrote:
> Hi Bjorn,
>
> Thank you for your review!
>
> > From: Bjorn Helgaas, Sent: Wednesday, September 21, 2022 5:08 AM
> >
> > On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote:
> > > Add macros defining Maximum Link Width bits in Link Capabilities
> > > Register.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > ---
> > > include/uapi/linux/pci_regs.h | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > > index 57b8e2ffb1dd..c9f4c452e210 100644
> > > --- a/include/uapi/linux/pci_regs.h
> > > +++ b/include/uapi/linux/pci_regs.h
> > > @@ -538,6 +538,13 @@
> > > #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
> > > #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
> > > #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> > > +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
> > > +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
> > > +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
> > > +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
> > > +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
> > > +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
> > > +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
> >
> > In PCIe r6.0, x32 is mentioned a few times, but not actually defined
> > for Link Capabilities. Has it been defined in an ECN or something?
>
> I should have looked PCIe r6.0, but I looked PCIe r4.0 v1.0 and it mentioned x32.
> So, I wrote the x32 macro.
Sure enough. It's there in r4.0 and r5.0, but dropped from r6.0.
Wish there were a git tree where we could see whether this was a
mistake or there was some reason for it. Maybe nobody had actually
built x32 hardware and they wanted to reserve the flexibility for
something else.
> I'll drop PCI_EXP_LNKCAP_MLW_X32 on v6 patch.
When you do, add my:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros
2022-09-21 2:22 ` Bjorn Helgaas
@ 2022-09-21 8:50 ` Yoshihiro Shimoda
0 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-21 8:50 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
Hi Bjorn,
> From: Bjorn Helgaas, Sent: Wednesday, September 21, 2022 11:22 AM
>
> On Wed, Sep 21, 2022 at 12:05:26AM +0000, Yoshihiro Shimoda wrote:
> > Hi Bjorn,
> > > From: Bjorn Helgaas, Sent: Wednesday, September 21, 2022 5:08 AM
> > >
> > > On Mon, Sep 05, 2022 at 04:12:48PM +0900, Yoshihiro Shimoda wrote:
> > > > Add macros defining Maximum Link Width bits in Link Capabilities
> > > > Register.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > ---
> > > > include/uapi/linux/pci_regs.h | 7 +++++++
> > > > 1 file changed, 7 insertions(+)
> > > >
> > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > > > index 57b8e2ffb1dd..c9f4c452e210 100644
> > > > --- a/include/uapi/linux/pci_regs.h
> > > > +++ b/include/uapi/linux/pci_regs.h
> > > > @@ -538,6 +538,13 @@
> > > > #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
> > > > #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
> > > > #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */
> > > > +#define PCI_EXP_LNKCAP_MLW_X32 0x00000200 /* Maximum Link Width x32 */
> > >
> > > In PCIe r6.0, x32 is mentioned a few times, but not actually defined
> > > for Link Capabilities. Has it been defined in an ECN or something?
> >
> > I should have looked PCIe r6.0, but I looked PCIe r4.0 v1.0 and it mentioned x32.
> > So, I wrote the x32 macro.
>
> Sure enough. It's there in r4.0 and r5.0, but dropped from r6.0.
> Wish there were a git tree where we could see whether this was a
> mistake or there was some reason for it. Maybe nobody had actually
> built x32 hardware and they wanted to reserve the flexibility for
> something else.
I understood it.
> > I'll drop PCI_EXP_LNKCAP_MLW_X32 on v6 patch.
>
> When you do, add my:
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thank you! I'll submit v6 patches tomorrow (or later).
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (2 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 03/12] PCI: Add PCI_EXP_LNKCAP_MLW macros Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-20 20:00 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
` (7 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Expose dw_pcie_ep_exit() to module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1a9956692a97..ca8f1804ee10 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -622,6 +622,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc);
}
+EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module
2022-09-05 7:12 ` [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
@ 2022-09-20 20:00 ` Bjorn Helgaas
0 siblings, 0 replies; 22+ messages in thread
From: Bjorn Helgaas @ 2022-09-20 20:00 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
Use "git log --oneline" and copy the prefix style.
On Mon, Sep 05, 2022 at 04:12:49PM +0900, Yoshihiro Shimoda wrote:
> Expose dw_pcie_ep_exit() to module.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (3 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 04/12] PCI: controller: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-20 20:03 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 06/12] PCI: dwc: Add reset_all_bars flag Yoshihiro Shimoda
` (6 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Some PCIe endpoint controller needs vendor-specific initialization
before the common code initialization. Add a nwe callback function
ep_pre_init() for it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index ca8f1804ee10..1b7e9e1b8d52 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -709,6 +709,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_version_detect(pci);
+ if (ep->ops->ep_pre_init)
+ ep->ops->ep_pre_init(ep);
+
dw_pcie_iatu_detect(pci);
ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index b541f653c209..9ed9621a12e4 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -317,6 +317,7 @@ struct dw_pcie_rp {
};
struct dw_pcie_ep_ops {
+ void (*ep_pre_init)(struct dw_pcie_ep *ep);
void (*ep_init)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type, u16 interrupt_num);
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops
2022-09-05 7:12 ` [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
@ 2022-09-20 20:03 ` Bjorn Helgaas
0 siblings, 0 replies; 22+ messages in thread
From: Bjorn Helgaas @ 2022-09-20 20:03 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
"PCI: designware-ep" in the prefix, since this is specific to ep.
There are several "PCI: dwc" prefixes, but those are typically things
that affect several dwc-based drivers.
On Mon, Sep 05, 2022 at 04:12:50PM +0900, Yoshihiro Shimoda wrote:
> Some PCIe endpoint controller needs vendor-specific initialization
> before the common code initialization. Add a nwe callback function
> ep_pre_init() for it.
s/Some ... controller needs/Some ... controllers need/
s/nwe/new/
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 06/12] PCI: dwc: Add reset_all_bars flag
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (4 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 05/12] PCI: dwc: Add ep_pre_init() callback to dw_pcie_ep_ops Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists Yoshihiro Shimoda
` (5 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Some PCIe endpoint drivers reset all BARs in each ep_init() ops.
So, we can reset the BARs into the common code if the flag is set.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1b7e9e1b8d52..a79482824e74 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -83,6 +83,14 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
+static void dw_pcie_ep_reset_all_bars(struct dw_pcie *pci)
+{
+ enum pci_barno bar;
+
+ for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+}
+
static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
u8 cap_ptr, u8 cap)
{
@@ -759,6 +767,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ep->ops->ep_init)
ep->ops->ep_init(ep);
+ if (ep->reset_all_bars)
+ dw_pcie_ep_reset_all_bars(pci);
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
ep->page_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9ed9621a12e4..0ad9ed77affb 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -353,6 +353,7 @@ struct dw_pcie_ep {
void __iomem *msi_mem;
phys_addr_t msi_mem_phys;
struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
+ bool reset_all_bars;
};
struct dw_pcie_ops {
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (5 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 06/12] PCI: dwc: Add reset_all_bars flag Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 8:39 ` Sergei Shtylyov
2022-09-05 7:12 ` [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
` (4 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Since reading value of PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL was
0x00000000 on one of SoCs (R-Car S4-8), it cannot find the eDMA.
So, directly read the eDMA register if edma.red_base is not zero.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 72f9620a374d..08f91a6bbe4b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -844,8 +844,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
{
u32 val;
- val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
- if (val == 0xFFFFFFFF && pci->edma.reg_base) {
+ if (pci->edma.reg_base) {
pci->edma.mf = EDMA_MF_EDMA_UNROLL;
val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
@@ -853,6 +852,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
pci->edma.mf = EDMA_MF_EDMA_LEGACY;
pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE;
+ val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
} else {
return -ENODEV;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists
2022-09-05 7:12 ` [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists Yoshihiro Shimoda
@ 2022-09-05 8:39 ` Sergei Shtylyov
2022-09-05 13:13 ` Yoshihiro Shimoda
0 siblings, 1 reply; 22+ messages in thread
From: Sergei Shtylyov @ 2022-09-05 8:39 UTC (permalink / raw)
To: Yoshihiro Shimoda, lpieralisi, robh+dt, kw, bhelgaas, krzk+dt,
geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc
Hello!
On 9/5/22 10:12 AM, Yoshihiro Shimoda wrote:
> Since reading value of PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL was
> 0x00000000 on one of SoCs (R-Car S4-8), it cannot find the eDMA.
> So, directly read the eDMA register if edma.red_base is not zero.
s/red/reg/?
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 72f9620a374d..08f91a6bbe4b 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -844,8 +844,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> {
> u32 val;
>
> - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> - if (val == 0xFFFFFFFF && pci->edma.reg_base) {
> + if (pci->edma.reg_base) {
> pci->edma.mf = EDMA_MF_EDMA_UNROLL;
>
> val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 22+ messages in thread* RE: [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists
2022-09-05 8:39 ` Sergei Shtylyov
@ 2022-09-05 13:13 ` Yoshihiro Shimoda
0 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 13:13 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm
Hello Sergei-san,
> From: Sergei Shtylyov, Sent: Monday, September 5, 2022 5:40 PM
>
> Hello!
>
> On 9/5/22 10:12 AM, Yoshihiro Shimoda wrote:
>
> > Since reading value of PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL was
> > 0x00000000 on one of SoCs (R-Car S4-8), it cannot find the eDMA.
> > So, directly read the eDMA register if edma.red_base is not zero.
>
> s/red/reg/?
Thank you for your review! I'll fix it.
Best regards,
Yoshihiro Shimoda
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 72f9620a374d..08f91a6bbe4b 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -844,8 +844,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> > {
> > u32 val;
> >
> > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> > - if (val == 0xFFFFFFFF && pci->edma.reg_base) {
> > + if (pci->edma.reg_base) {
> > pci->edma.mf = EDMA_MF_EDMA_UNROLL;
> >
> > val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
> [...]
>
> MBR, Sergey
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (6 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 07/12] PCI: dwc: Avoid reading a register to detect whether eDMA exists Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-20 19:59 ` Bjorn Helgaas
2022-09-05 7:12 ` [PATCH v5 09/12] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
` (3 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add R-Car Gen4 PCIe Host support. This controller is based on
Synopsys DesignWare PCIe.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile | 2 +
.../pci/controller/dwc/pcie-rcar-gen4-host.c | 195 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 181 ++++++++++++++++
drivers/pci/controller/dwc/pcie-rcar-gen4.h | 63 ++++++
5 files changed, 450 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 771b8b146623..99717b0f4e50 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -393,4 +393,13 @@ config PCIE_FU740
Say Y here if you want PCIe controller support for the SiFive
FU740.
+config PCIE_RCAR_GEN4
+ tristate "Renesas R-Car Gen4 PCIe Host controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
+ This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index bf5c311875a1..486cf706b53d 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
+pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
+obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
new file mode 100644
index 000000000000..89b1c50bf00d
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+ u32 val;
+
+ rcar_gen4_pcie_set_device_type(rcar, true, dw->num_lanes);
+
+ dw_pcie_dbi_ro_wr_en(dw);
+
+ /* Enable L1 Substates */
+ val = dw_pcie_readl_dbi(dw, L1PSCAP(PCI_L1SS_CTL1));
+ val &= ~PCI_L1SS_CTL1_L1SS_MASK;
+ val |= PCI_L1SS_CTL1_PCIPM_L1_2 | PCI_L1SS_CTL1_PCIPM_L1_1 |
+ PCI_L1SS_CTL1_ASPM_L1_2 | PCI_L1SS_CTL1_ASPM_L1_1;
+ dw_pcie_writel_dbi(dw, L1PSCAP(PCI_L1SS_CTL1), val);
+
+ rcar_gen4_pcie_disable_bar(dw, BAR0MASKF);
+ rcar_gen4_pcie_disable_bar(dw, BAR1MASKF);
+
+ /* Set Root Control */
+ val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_RTCTL));
+ val |= PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
+ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
+ PCI_EXP_RTCTL_CRSSVE;
+ dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_RTCTL), val);
+
+ /* Set Interrupt Disable, SERR# Enable, Parity Error Response */
+ val = dw_pcie_readl_dbi(dw, PCI_COMMAND);
+ val |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+ PCI_COMMAND_INTX_DISABLE;
+ dw_pcie_writel_dbi(dw, PCI_COMMAND, val);
+
+ /* Enable SERR */
+ val = dw_pcie_readb_dbi(dw, PCI_BRIDGE_CONTROL);
+ val |= PCI_BRIDGE_CTL_SERR;
+ dw_pcie_writeb_dbi(dw, PCI_BRIDGE_CONTROL, val);
+
+ /* Device control */
+ val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_DEVCTL));
+ val |= PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
+ PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE;
+ dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_DEVCTL), val);
+
+ dw_pcie_dbi_ro_wr_dis(dw);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ /* Enable MSI interrupt signal */
+ val = readl(rcar->base + PCIEINTSTS0EN);
+ val |= MSI_CTRL_INT;
+ writel(val, rcar->base + PCIEINTSTS0EN);
+ }
+
+ dw_pcie_setup_rc(pp);
+
+ dw_pcie_dbi_ro_wr_en(dw);
+ rcar_gen4_pcie_set_max_link_width(dw, dw->num_lanes);
+ dw_pcie_dbi_ro_wr_dis(dw);
+
+ if (!dw_pcie_link_up(dw)) {
+ ret = dw->ops->start_link(dw);
+ if (ret)
+ return ret;
+ }
+
+ /* Ignore errors, the link may come up later */
+ if (dw_pcie_wait_for_link(dw))
+ dev_info(dw->dev, "PCIe link down\n");
+
+ return 0;
+}
+
+static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
+ .host_init = rcar_gen4_pcie_host_init,
+};
+
+static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ struct dw_pcie_rp *pp = &dw->pp;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ pp->msi_irq[0] = platform_get_irq_byname(pdev, "others");
+ if (pp->msi_irq[0] < 0)
+ return pp->msi_irq[0];
+ }
+
+ pp->ops = &rcar_gen4_pcie_host_ops;
+
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_host_deinit(&rcar->dw.pp);
+}
+
+static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *dw = &rcar->dw;
+
+ /* Renesas-specific registers */
+ rcar->base = devm_platform_ioremap_resource_byname(pdev, "app");
+ if (IS_ERR(rcar->base))
+ return PTR_ERR(rcar->base);
+
+ return rcar_gen4_pcie_devm_reset_get(rcar, dw->dev);
+}
+
+static int rcar_gen4_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+ int err;
+
+ rcar = rcar_gen4_pcie_devm_alloc(dev);
+ if (!rcar)
+ return -ENOMEM;
+
+ err = rcar_gen4_pcie_get_resources(rcar, pdev);
+ if (err < 0) {
+ dev_err(dev, "failed to request resource: %d\n", err);
+ return err;
+ }
+
+ platform_set_drvdata(pdev, rcar);
+
+ err = rcar_gen4_pcie_prepare(rcar);
+ if (err < 0)
+ return err;
+
+ err = rcar_gen4_add_dw_pcie_rp(rcar, pdev);
+ if (err < 0)
+ goto err_add;
+
+ return 0;
+
+err_add:
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return err;
+}
+
+static int rcar_gen4_pcie_remove(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
+
+ rcar_gen4_remove_dw_pcie_rp(rcar);
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return 0;
+}
+
+static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ { .compatible = "renesas,rcar-gen4-pcie", },
+ {},
+};
+
+static struct platform_driver rcar_gen4_pcie_driver = {
+ .driver = {
+ .name = "pcie-rcar-gen4",
+ .of_match_table = rcar_gen4_pcie_of_match,
+ },
+ .probe = rcar_gen4_pcie_probe,
+ .remove = rcar_gen4_pcie_remove,
+};
+module_platform_driver(rcar_gen4_pcie_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
new file mode 100644
index 000000000000..b3d37c88c400
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+/* Renesas-specific */
+#define PCIERSTCTRL1 0x0014
+#define APP_HOLD_PHY_RST BIT(16)
+#define APP_LTSSM_ENABLE BIT(0)
+
+#define DWC_VERSION 0x520a
+
+static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
+ bool enable)
+{
+ u32 val;
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ if (enable) {
+ val |= APP_LTSSM_ENABLE;
+ val &= ~APP_HOLD_PHY_RST;
+ } else {
+ val &= ~APP_LTSSM_ENABLE;
+ val |= APP_HOLD_PHY_RST;
+ }
+ writel(val, rcar->base + PCIERSTCTRL1);
+}
+
+static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ u32 val, mask;
+
+ val = readl(rcar->base + PCIEINTSTS0);
+ mask = RDLH_LINK_UP | SMLH_LINK_UP;
+
+ return (val & mask) == mask;
+}
+
+static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ rcar_gen4_pcie_ltssm_enable(rcar, true);
+
+ return 0;
+}
+
+static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ rcar_gen4_pcie_ltssm_enable(rcar, false);
+}
+
+void rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc,
+ int num_lanes)
+{
+ u32 val;
+
+ val = readl(rcar->base + PCIEMSR0);
+ if (rc)
+ val |= DEVICE_TYPE_RC;
+ else
+ val |= DEVICE_TYPE_EP;
+ if (num_lanes < 4)
+ val |= BIFUR_MOD_SET_ON;
+ writel(val, rcar->base + PCIEMSR0);
+}
+
+void rcar_gen4_pcie_disable_bar(struct dw_pcie *dw, u32 bar_mask_reg)
+{
+ dw_pcie_writel_dbi(dw, SHADOW_REG(bar_mask_reg), 0x0);
+}
+
+void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *dw, int num_lanes)
+{
+ u32 val = dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCAP));
+
+ val &= ~PCI_EXP_LNKCAP_MLW;
+ switch (num_lanes) {
+ case 1:
+ val |= PCI_EXP_LNKCAP_MLW_X1;
+ break;
+ case 2:
+ val |= PCI_EXP_LNKCAP_MLW_X2;
+ break;
+ case 4:
+ val |= PCI_EXP_LNKCAP_MLW_X4;
+ break;
+ default:
+ dev_info(dw->dev, "invalid num-lanes %d\n", num_lanes);
+ val |= PCI_EXP_LNKCAP_MLW_X1;
+ break;
+ }
+ dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_LNKCAP), val);
+}
+
+int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+ int err;
+
+ pm_runtime_enable(dev);
+ err = pm_runtime_resume_and_get(dev);
+ if (err < 0) {
+ dev_err(dev, "%s: failed to resume/get Runtime PM\n", __func__);
+ goto err_resume_and_get;
+ }
+
+ err = reset_control_deassert(rcar->rst);
+ if (err < 0) {
+ dev_err(dev, "%s: failed to deassert reset_control\n", __func__);
+ goto err_deassert;
+ }
+
+ writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
+
+ return 0;
+
+err_deassert:
+ pm_runtime_put(dev);
+
+err_resume_and_get:
+ pm_runtime_disable(dev);
+
+ return err;
+}
+
+void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+
+ writel(0, rcar->base + PCIEDMAINTSTSEN);
+ reset_control_assert(rcar->rst);
+ pm_runtime_put(dev);
+ pm_runtime_disable(dev);
+}
+
+int rcar_gen4_pcie_devm_reset_get(struct rcar_gen4_pcie *rcar,
+ struct device *dev)
+{
+ rcar->rst = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(rcar->rst)) {
+ dev_err(dev, "failed to get Cold-reset\n");
+ return PTR_ERR(rcar->rst);
+ }
+
+ return 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = rcar_gen4_pcie_start_link,
+ .stop_link = rcar_gen4_pcie_stop_link,
+ .link_up = rcar_gen4_pcie_link_up,
+};
+
+struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev)
+{
+ struct rcar_gen4_pcie *rcar;
+
+ rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
+ if (!rcar)
+ return NULL;
+
+ rcar->dw.dev = dev;
+ rcar->dw.ops = &dw_pcie_ops;
+ rcar->dw.version = DWC_VERSION;
+
+ return rcar;
+}
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
new file mode 100644
index 000000000000..19c5fd56a8f9
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#ifndef _PCIE_RCAR_GEN4_H_
+#define _PCIE_RCAR_GEN4_H_
+
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/reset.h>
+
+#include "pcie-designware.h"
+
+/* PCI Express capability */
+#define EXPCAP(x) (0x0070 + (x))
+/* ASPM L1 PM Substates */
+#define L1PSCAP(x) (0x01bc + (x))
+/* PCI Shadow offset */
+#define SHADOW_REG(x) (0x2000 + (x))
+/* BAR Mask registers */
+#define BAR0MASKF 0x0010
+#define BAR1MASKF 0x0014
+#define BAR2MASKF 0x0018
+#define BAR3MASKF 0x001c
+#define BAR4MASKF 0x0020
+#define BAR5MASKF 0x0024
+
+/* Renesas-specific */
+#define PCIEMSR0 0x0000
+#define BIFUR_MOD_SET_ON BIT(0)
+#define DEVICE_TYPE_EP 0
+#define DEVICE_TYPE_RC BIT(4)
+
+#define PCIEINTSTS0 0x0084
+#define PCIEINTSTS0EN 0x0310
+#define MSI_CTRL_INT BIT(26)
+#define SMLH_LINK_UP BIT(7)
+#define RDLH_LINK_UP BIT(6)
+#define PCIEDMAINTSTSEN 0x0314
+#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
+
+struct rcar_gen4_pcie {
+ struct dw_pcie dw;
+ void __iomem *base;
+ struct reset_control *rst;
+};
+#define to_rcar_gen4_pcie(x) dev_get_drvdata((x)->dev)
+
+u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg);
+void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val);
+void rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc,
+ int num_lanes);
+void rcar_gen4_pcie_disable_bar(struct dw_pcie *dw, u32 bar_mask_reg);
+void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *pci, int num_lanes);
+int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie);
+void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie);
+int rcar_gen4_pcie_devm_reset_get(struct rcar_gen4_pcie *pcie,
+ struct device *dev);
+struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev);
+
+#endif /* _PCIE_RCAR_GEN4_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support
2022-09-05 7:12 ` [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
@ 2022-09-20 19:59 ` Bjorn Helgaas
0 siblings, 0 replies; 22+ messages in thread
From: Bjorn Helgaas @ 2022-09-20 19:59 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas,
magnus.damm, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
"PCI: renesas" is too general for the subject line. The typical
pattern would be "PCI: rcar-gen4" for the host driver and "PCI:
rcar-gen4-ep" for the endpoint driver.
On Mon, Sep 05, 2022 at 04:12:53PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe Host support. This controller is based on
> Synopsys DesignWare PCIe.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v5 09/12] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (7 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 08/12] PCI: renesas: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 10/12] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
` (2 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add R-Car Gen4 PCIe Endpoint support. This controller is based on
Synopsys DesignWare PCIe.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile | 2 +
.../pci/controller/dwc/pcie-rcar-gen4-ep.c | 182 ++++++++++++++++++
3 files changed, 193 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 99717b0f4e50..4889bde3471b 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -402,4 +402,13 @@ config PCIE_RCAR_GEN4
Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
This uses the DesignWare core.
+config PCIE_RCAR_GEN4_EP
+ tristate "Renesas R-Car Gen4 PCIe Endpoint controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ help
+ Say Y here if you want PCIe endpoint controller support on R-Car Gen4
+ SoCs. This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 486cf706b53d..0fb0bde26ac4 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
+pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o
+obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
new file mode 100644
index 000000000000..79677cf40ebf
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+/* Configuration */
+#define PCICONF3 0x000c
+#define MULTI_FUNC BIT(23)
+
+static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int val;
+
+ rcar_gen4_pcie_set_device_type(rcar, false, dw->num_lanes);
+
+ dw_pcie_dbi_ro_wr_en(dw);
+
+ /* Single function */
+ val = dw_pcie_readl_dbi(dw, PCICONF3);
+ val &= ~MULTI_FUNC;
+ dw_pcie_writel_dbi(dw, PCICONF3, val);
+
+ rcar_gen4_pcie_disable_bar(dw, BAR2MASKF);
+ rcar_gen4_pcie_disable_bar(dw, BAR3MASKF);
+
+ rcar_gen4_pcie_set_max_link_width(dw, dw->num_lanes);
+
+ dw_pcie_dbi_ro_wr_dis(dw);
+}
+
+static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ case PCI_EPC_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(dw->dev, "UNKNOWN IRQ type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .align = SZ_1M,
+};
+
+static const struct pci_epc_features*
+rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
+{
+ return &rcar_gen4_pcie_epc_features;
+}
+
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
+ .ep_pre_init = rcar_gen4_pcie_ep_pre_init,
+ .raise_irq = rcar_gen4_pcie_ep_raise_irq,
+ .get_features = rcar_gen4_pcie_ep_get_features,
+};
+
+static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ struct dw_pcie_ep *ep;
+ int ret;
+
+ ep = &dw->ep;
+ ep->ops = &pcie_ep_ops;
+ ep->reset_all_bars = true;
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+
+ dw->ops->start_link(dw);
+
+ return 0;
+}
+
+static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_ep_exit(&rcar->dw.ep);
+}
+
+static int rcar_gen4_pcie_ep_get_resources(struct rcar_gen4_pcie *rcar,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ struct device *dev = dw->dev;
+
+ /* Renesas-specific registers */
+ rcar->base = devm_platform_ioremap_resource_byname(pdev, "appl");
+ if (IS_ERR(rcar->base))
+ return PTR_ERR(rcar->base);
+
+ return rcar_gen4_pcie_devm_reset_get(rcar, dev);
+}
+
+static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+ int err;
+
+ rcar = rcar_gen4_pcie_devm_alloc(dev);
+ if (!rcar)
+ return -ENOMEM;
+
+ err = rcar_gen4_pcie_ep_get_resources(rcar, pdev);
+ if (err < 0) {
+ dev_err(dev, "failed to request resource: %d\n", err);
+ return err;
+ }
+
+ platform_set_drvdata(pdev, rcar);
+
+ err = rcar_gen4_pcie_prepare(rcar);
+ if (err < 0)
+ return err;
+
+ err = rcar_gen4_add_pcie_ep(rcar, pdev);
+ if (err < 0)
+ goto err_add;
+
+ return 0;
+
+err_add:
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return err;
+}
+
+static int rcar_gen4_pcie_ep_remove(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
+
+ rcar_gen4_remove_pcie_ep(rcar);
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return 0;
+}
+
+static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ { .compatible = "renesas,rcar-gen4-pcie-ep", },
+ {},
+};
+
+static struct platform_driver rcar_gen4_pcie_ep_driver = {
+ .driver = {
+ .name = "pcie-rcar-gen4-ep",
+ .of_match_table = rcar_gen4_pcie_of_match,
+ },
+ .probe = rcar_gen4_pcie_ep_probe,
+ .remove = rcar_gen4_pcie_ep_remove,
+};
+module_platform_driver(rcar_gen4_pcie_ep_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 10/12] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (8 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 09/12] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 11/12] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 12/12] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Update this entry for R-Car Gen4's source code.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 41762df1be0c..badf376ab3df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15704,6 +15704,7 @@ L: linux-renesas-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/*rcar*
F: drivers/pci/controller/*rcar*
+F: drivers/pci/controller/dwc/*rcar*
PCI DRIVER FOR SAMSUNG EXYNOS
M: Jingoo Han <jingoohan1@gmail.com>
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 11/12] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (9 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 10/12] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
2022-09-05 7:12 ` [PATCH v5 12/12] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 122 ++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index c2f152bcf10e..883e09ba1fa1 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -639,6 +639,128 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
+ pciec0: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>,
+ <0 0xe65d5000 0 0x1200>, <0 0xe65d6200 0 0x0e00>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable",
+ "fatal", "nonfatal", "lp", "vndmsg";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <2>;
+ status = "disabled";
+ };
+
+ pciec1: pcie@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>,
+ <0 0xe65dd000 0 0x1200>, <0 0xe65de200 0 0x0e00>,
+ <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable",
+ "fatal", "nonfatal", "lp", "vndmsg";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <2>;
+ status = "disabled";
+ };
+
+ pciec0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>,
+ <0 0xe65d5000 0 0x1200>, <0 0xe65d6200 0 0x0e00>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "atu", "dma", "appl", "addr_space";
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable",
+ "fatal", "nonfatal", "lp", "vndmsg";
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ max-link-speed = <2>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>,
+ <0 0xe65dd000 0 0x1200>, <0 0xe65de200 0 0x0e00>,
+ <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "atu", "dma", "appl", "addr_space";
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "others", "dma", "correctable",
+ "fatal", "nonfatal", "lp", "vndmsg";
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ num-lanes = <2>;
+ max-link-speed = <2>;
+ status = "disabled";
+ };
+
ufs: ufs@e6860000 {
compatible = "renesas,r8a779f0-ufs";
reg = <0 0xe6860000 0 0x100>;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v5 12/12] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
2022-09-05 7:12 [PATCH v5 00/12] treewide: PCI: renesas: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (10 preceding siblings ...)
2022-09-05 7:12 ` [PATCH v5 11/12] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2022-09-05 7:12 ` Yoshihiro Shimoda
11 siblings, 0 replies; 22+ messages in thread
From: Yoshihiro Shimoda @ 2022-09-05 7:12 UTC (permalink / raw)
To: lpieralisi, robh+dt, kw, bhelgaas, krzk+dt, geert+renesas, magnus.damm
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 4a876d47f59b..b1d0f7c4fd6b 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
+#include <dt-bindings/gpio/gpio.h>
#include "r8a779f0.dtsi"
/ {
@@ -49,6 +50,28 @@ &extalr_clk {
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ gpio_exp_20: gpio@20 {
+ compatible = "ti,tca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pcie-perst-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "PCIE_PERSTn";
+ };
+ };
+};
+
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
@@ -85,10 +108,21 @@ &mmc0 {
status = "okay";
};
+&pciec0 {
+ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
@@ -100,6 +134,11 @@ mmc_pins: mmc {
power-source = <1800>;
};
+ pcie0_pins: pcie0 {
+ groups = "pcie0_clkreq_n";
+ function = "pcie";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread