* [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
@ 2022-09-20 18:48 ` Prabhakar
2022-09-22 12:54 ` Krzysztof Kozlowski
2022-10-28 12:44 ` Geert Uytterhoeven
2022-09-20 18:48 ` [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
` (9 subsequent siblings)
10 siblings, 2 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
to the soc/renesas folder instead. This is in preparation for adding a new
SoC (RZ/Five) from Renesas which is based on RISC-V.
While at it drop the old entry for renesas.yaml from MAINTAINERS file and
there is no need to update the new file path of renesas.yaml as we already
have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3 -> v4
* Updated the path in the DT binding
* Included RB tag from Geert
v3:
* New patch along with this series previously posted as a standalone
patch [0].
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220815111708.22302-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
---
.../devicetree/bindings/{arm => soc/renesas}/renesas.yaml | 2 +-
MAINTAINERS | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (99%)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/arm/renesas.yaml
rename to Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index f51464a08aff..07c5e6ebd5a0 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/renesas.yaml#
+$id: http://devicetree.org/schemas/soc/renesas/renesas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas SH-Mobile, R-Mobile, and R-Car Platform
diff --git a/MAINTAINERS b/MAINTAINERS
index d71b20527224..48c5a152f743 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2679,7 +2679,6 @@ S: Supported
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
C: irc://irc.libera.chat/renesas-soc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
-F: Documentation/devicetree/bindings/arm/renesas.yaml
F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml
F: Documentation/devicetree/bindings/soc/renesas/
F: arch/arm/boot/dts/emev2*
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
@ 2022-09-22 12:54 ` Krzysztof Kozlowski
2022-10-28 12:44 ` Geert Uytterhoeven
1 sibling, 0 replies; 26+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-22 12:54 UTC (permalink / raw)
To: Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
On 20/09/2022 20:48, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
> is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
> to the soc/renesas folder instead. This is in preparation for adding a new
> SoC (RZ/Five) from Renesas which is based on RISC-V.
>
> While at it drop the old entry for renesas.yaml from MAINTAINERS file and
> there is no need to update the new file path of renesas.yaml as we already
> have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-22 12:54 ` Krzysztof Kozlowski
@ 2022-10-28 12:44 ` Geert Uytterhoeven
1 sibling, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2022-10-28 12:44 UTC (permalink / raw)
To: Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
On Tue, Sep 20, 2022 at 8:50 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
> is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
> to the soc/renesas folder instead. This is in preparation for adding a new
> SoC (RZ/Five) from Renesas which is based on RISC-V.
>
> While at it drop the old entry for renesas.yaml from MAINTAINERS file and
> there is no need to update the new file path of renesas.yaml as we already
> have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3 -> v4
> * Updated the path in the DT binding
> * Included RB tag from Geert
Will queue in renesas-devel for v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
@ 2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
` (8 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-20 18:48 ` [PATCH v4 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-20 18:48 ` [PATCH v4 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
@ 2022-09-20 18:48 ` Prabhakar
2022-09-20 18:48 ` [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
` (7 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3 -> v4
* No change
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included ack from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2a1c5ae5b0aa..1681767790c5 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (2 preceding siblings ...)
2022-09-20 18:48 ` [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
@ 2022-09-20 18:48 ` Prabhakar
2022-10-28 12:46 ` Geert Uytterhoeven
2022-09-20 18:48 ` [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
` (6 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar, Krzysztof Kozlowski
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Document Renesas RZ/Five (R9A07G043) SoC.
More info about RZ/Five SoC:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3 -> v4
* No change
v2 -> v3
* Dropped "(RISC-V core)" comment
* Included ACK and RB tags
v1 -> v2
* New patch
---
Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 07c5e6ebd5a0..2789022b52eb 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -431,11 +431,12 @@ properties:
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- const: renesas,r9a06g032
- - description: RZ/G2UL (R9A07G043)
+ - description: RZ/Five and RZ/G2UL (R9A07G043)
items:
- enum:
- renesas,smarc-evk # SMARC EVK
- enum:
+ - renesas,r9a07g043f01 # RZ/Five
- renesas,r9a07g043u11 # RZ/G2UL Type-1
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
2022-09-20 18:48 ` [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
@ 2022-10-28 12:46 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2022-10-28 12:46 UTC (permalink / raw)
To: Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar, Krzysztof Kozlowski
On Tue, Sep 20, 2022 at 8:50 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document Renesas RZ/Five (R9A07G043) SoC.
>
> More info about RZ/Five SoC:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3 -> v4
> * No change
Will queue in renesas-devel for v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (3 preceding siblings ...)
2022-09-20 18:48 ` [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
@ 2022-09-20 18:48 ` Prabhakar
2022-09-20 19:04 ` Conor Dooley
2022-09-20 18:49 ` [PATCH v4 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
` (5 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3 -> v4
* Dropped SOC_RENESAS_RZFIVE config option
* Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
under ARCH_RENESAS
* Updated commit message
* Dropped RB tag
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* No Change
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..5c420ed55ef9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
endif # SOC_CANAAN
+config ARCH_RENESAS
+ bool "Renesas RISC-V SoCs"
+ help
+ This enables support for the RISC-V based Renesas SoCs.
+
endmenu # "SoC selection"
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-09-20 18:48 ` [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
@ 2022-09-20 19:04 ` Conor Dooley
2022-09-20 21:04 ` Lad, Prabhakar
0 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2022-09-20 19:04 UTC (permalink / raw)
To: Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
On Tue, Sep 20, 2022 at 07:48:59PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3 -> v4
> * Dropped SOC_RENESAS_RZFIVE config option
> * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> under ARCH_RENESAS
> * Updated commit message
> * Dropped RB tag
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * No Change
> ---
> arch/riscv/Kconfig.socs | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..5c420ed55ef9 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
> endif # SOC_CANAAN
I am not asking for a respin for this since no-one likely cares, but
I think a future goal would be to sort the file alphabetically. I'll
probably do it with the other 30-something patches my Kconfig.socs
rework series has got to now - but if you *are* respinning sorting
alphabetically (ignoring the CANAAN) would reduce future churn.
Thanks,
Conor.
>
> +config ARCH_RENESAS
> + bool "Renesas RISC-V SoCs"
> + help
> + This enables support for the RISC-V based Renesas SoCs.
> +
> endmenu # "SoC selection"
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-09-20 19:04 ` Conor Dooley
@ 2022-09-20 21:04 ` Lad, Prabhakar
2022-09-20 21:10 ` Conor Dooley
0 siblings, 1 reply; 26+ messages in thread
From: Lad, Prabhakar @ 2022-09-20 21:04 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
Hi Conor,
Thank you for the review.
On Tue, Sep 20, 2022 at 8:04 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Sep 20, 2022 at 07:48:59PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> > We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3 -> v4
> > * Dropped SOC_RENESAS_RZFIVE config option
> > * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> > under ARCH_RENESAS
> > * Updated commit message
> > * Dropped RB tag
> > * Used riscv instead of RISC-V in subject line
> >
> > v2 -> v3
> > * Included RB tag from Geert
> >
> > v1 -> v2
> > * No Change
> > ---
> > arch/riscv/Kconfig.socs | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..5c420ed55ef9 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> > endif # SOC_CANAAN
>
> I am not asking for a respin for this since no-one likely cares, but
> I think a future goal would be to sort the file alphabetically. I'll
> probably do it with the other 30-something patches my Kconfig.socs
> rework series has got to now - but if you *are* respinning sorting
> alphabetically (ignoring the CANAAN) would reduce future churn.
>
To clarify, shall I add ARCH_RENESAS to the beginning of the file or
after the SOC_MICROCHIP_POLARFIRE config?
As rest of the configs start with SOC and for Renesas it starts with
ARCH, so to avoid another re-spin hence this query.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
2022-09-20 21:04 ` Lad, Prabhakar
@ 2022-09-20 21:10 ` Conor Dooley
0 siblings, 0 replies; 26+ messages in thread
From: Conor Dooley @ 2022-09-20 21:10 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
On Tue, Sep 20, 2022 at 10:04:06PM +0100, Lad, Prabhakar wrote:
> To clarify, shall I add ARCH_RENESAS to the beginning of the file or
> after the SOC_MICROCHIP_POLARFIRE config?
>
> As rest of the configs start with SOC and for Renesas it starts with
> ARCH, so to avoid another re-spin hence this query.
I'd say sort it based on Renesas so that everything else can be swapped
over in place. I don't care that much to be honest, was just an "if
you're already respinning" kind of thing.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v4 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (4 preceding siblings ...)
2022-09-20 18:48 ` [PATCH v4 05/10] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
@ 2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes Prabhakar
` (4 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
v3 -> v4
* No change
v2 -> v3
* Fixed clock entry for CPU core
* Fixed timebase frequency to 12MHz
* Fixed sorting of the nodes
* Included RB tags
v1 -> v2
* Dropped including makefile change
* Updated ndev count
---
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 120 +++++++++++++++++++++
1 file changed, 120 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..fb6733f3cc2b
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <12000000>;
+
+ ax45mp: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+ <414 IRQ_TYPE_LEVEL_HIGH>,
+ <415 IRQ_TYPE_LEVEL_HIGH>,
+ <413 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g043-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 152>;
+ clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_GPIO_RSTN>,
+ <&cpg R9A07G043_GPIO_PORT_RESETN>,
+ <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+ };
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <512>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (5 preceding siblings ...)
2022-09-20 18:49 ` [PATCH v4 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
@ 2022-09-20 18:49 ` Prabhakar
2022-09-20 19:21 ` Biju Das
2022-09-20 18:49 ` [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
` (3 subsequent siblings)
10 siblings, 1 reply; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier board
DTSIs([0] and [1]).
As the RZ/G2UL SMARC EVK enables almost all the blocks supported by the
SoC and whereas for the RZ/Five SMARC EVK we will gradually be enabling
the blocks as a result we are adding the placeholder nodes to avoid DTB
compilation errors (currently we dont have support in DTC to delete the
reference nodes without actual nodes).
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3 -> v4
* Dropped status and reg-names properties
* Updated the commit message
* Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
enabled so added a placeholder for this too.
v2 -> v3
* New patch
---
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150 +++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
index fb6733f3cc2b..d90d263b1b13 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -13,6 +13,14 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ audio_clk1: audio1-clk {
+ /* placeholder */
+ };
+
+ audio_clk2: audio2-clk {
+ /* placeholder */
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -54,6 +62,19 @@ soc: soc {
#size-cells = <2>;
ranges;
+ ssi1: ssi@1004a000 {
+ reg = <0 0x1004a000 0 0x400>;
+ #sound-dai-cells = <0>;
+
+ /* placeholder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+
+ /* placeholder */
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
@@ -73,6 +94,41 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+
+ /* placeholder */
+ };
+
+ i2c0: i2c@10058000 {
+ reg = <0 0x10058000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* placeholder */
+ };
+
+ i2c1: i2c@10058400 {
+ reg = <0 0x10058400 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* placeholder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+
+ /* placeholder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+
+ /* placeholder */
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g043-cpg";
reg = <0 0x11010000 0 0x10000>;
@@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G043_GPIO_SPARE_RESETN>;
};
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+
+ /* placeholder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+
+ /* placeholder */
+ };
+
+ eth0: ethernet@11c20000 {
+ reg = <0 0x11c20000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* placeholder */
+ };
+
+ eth1: ethernet@11c30000 {
+ reg = <0 0x11c30000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* placeholder */
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+
+ /* placeholder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+
+ /* placeholder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+
+ /* placeholder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+
+ /* placeholder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+
+ /* placeholder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+
+ /* placeholder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+
+ /* placeholder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+
+ /* placeholder */
+ };
+
plic: interrupt-controller@12c00000 {
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
#interrupt-cells = <2>;
@@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+
+ /* placeholder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+
+ /* placeholder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+
+ /* placeholder */
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-20 18:49 ` [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes Prabhakar
@ 2022-09-20 19:21 ` Biju Das
2022-09-20 19:26 ` Biju Das
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2022-09-20 19:21 UTC (permalink / raw)
To: Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Prabhakar,
Thanks for the patch.
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
>
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTSIs([0] and [1]).
Just a question,
Why can't we reuse SoC dtsi as well, as 90% of the SoC nodes are same?
Split common stuff from arch/arm/boot/dts/renesas/r9a07g043.dtsi
and add ARM specific CPU, IRQ to arch/arm/boot/dts/renesas/r9a07g043u.dtsi
RISC-V specific CPU, IRQ to arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
Both r9a07g043{u,f} dtsi will add common dtsi.
Cheers,
Biju
>
> As the RZ/G2UL SMARC EVK enables almost all the blocks supported by
> the SoC and whereas for the RZ/Five SMARC EVK we will gradually be
> enabling the blocks as a result we are adding the placeholder nodes to
> avoid DTB compilation errors (currently we dont have support in DTC to
> delete the reference nodes without actual nodes).
>
> [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3 -> v4
> * Dropped status and reg-names properties
> * Updated the commit message
> * Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
> enabled so added a placeholder for this too.
>
> v2 -> v3
> * New patch
> ---
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150
> +++++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..d90d263b1b13 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + audio_clk1: audio1-clk {
> + /* placeholder */
> + };
> +
> + audio_clk2: audio2-clk {
> + /* placeholder */
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -54,6 +62,19 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> + ssi1: ssi@1004a000 {
> + reg = <0 0x1004a000 0 0x400>;
> + #sound-dai-cells = <0>;
> +
> + /* placeholder */
> + };
> +
> + spi1: spi@1004b000 {
> + reg = <0 0x1004b000 0 0x400>;
> +
> + /* placeholder */
> + };
> +
> scif0: serial@1004b800 {
> compatible = "renesas,scif-r9a07g043",
> "renesas,scif-r9a07g044";
> @@ -73,6 +94,41 @@ scif0: serial@1004b800 {
> status = "disabled";
> };
>
> + canfd: can@10050000 {
> + reg = <0 0x10050000 0 0x8000>;
> +
> + /* placeholder */
> + };
> +
> + i2c0: i2c@10058000 {
> + reg = <0 0x10058000 0 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + /* placeholder */
> + };
> +
> + i2c1: i2c@10058400 {
> + reg = <0 0x10058400 0 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* placeholder */
> + };
> +
> + adc: adc@10059000 {
> + reg = <0 0x10059000 0 0x400>;
> +
> + /* placeholder */
> + };
> +
> + sbc: spi@10060000 {
> + reg = <0 0x10060000 0 0x10000>,
> + <0 0x20000000 0 0x10000000>,
> + <0 0x10070000 0 0x10000>;
> +
> + /* placeholder */
> + };
> +
> cpg: clock-controller@11010000 {
> compatible = "renesas,r9a07g043-cpg";
> reg = <0 0x11010000 0 0x10000>;
> @@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
> <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> };
>
> + sdhi0: mmc@11c00000 {
> + reg = <0x0 0x11c00000 0 0x10000>;
> +
> + /* placeholder */
> + };
> +
> + sdhi1: mmc@11c10000 {
> + reg = <0x0 0x11c10000 0 0x10000>;
> +
> + /* placeholder */
> + };
> +
> + eth0: ethernet@11c20000 {
> + reg = <0 0x11c20000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* placeholder */
> + };
> +
> + eth1: ethernet@11c30000 {
> + reg = <0 0x11c30000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* placeholder */
> + };
> +
> + phyrst: usbphy-ctrl@11c40000 {
> + reg = <0 0x11c40000 0 0x10000>;
> +
> + /* placeholder */
> + };
> +
> + ohci0: usb@11c50000 {
> + reg = <0 0x11c50000 0 0x100>;
> +
> + /* placeholder */
> + };
> +
> + ohci1: usb@11c70000 {
> + reg = <0 0x11c70000 0 0x100>;
> +
> + /* placeholder */
> + };
> +
> + ehci0: usb@11c50100 {
> + reg = <0 0x11c50100 0 0x100>;
> +
> + /* placeholder */
> + };
> +
> + ehci1: usb@11c70100 {
> + reg = <0 0x11c70100 0 0x100>;
> +
> + /* placeholder */
> + };
> +
> + usb2_phy0: usb-phy@11c50200 {
> + reg = <0 0x11c50200 0 0x700>;
> +
> + /* placeholder */
> + };
> +
> + usb2_phy1: usb-phy@11c70200 {
> + reg = <0 0x11c70200 0 0x700>;
> +
> + /* placeholder */
> + };
> +
> + hsusb: usb@11c60000 {
> + reg = <0 0x11c60000 0 0x10000>;
> +
> + /* placeholder */
> + };
> +
> plic: interrupt-controller@12c00000 {
> compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
> #interrupt-cells = <2>;
> @@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> };
> +
> + wdt0: watchdog@12800800 {
> + reg = <0 0x12800800 0 0x400>;
> +
> + /* placeholder */
> + };
> +
> + ostm1: timer@12801400 {
> + reg = <0x0 0x12801400 0x0 0x400>;
> +
> + /* placeholder */
> + };
> +
> + ostm2: timer@12801800 {
> + reg = <0x0 0x12801800 0x0 0x400>;
> +
> + /* placeholder */
> + };
> };
> };
> --
> 2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-20 19:21 ` Biju Das
@ 2022-09-20 19:26 ` Biju Das
2022-09-20 20:51 ` Lad, Prabhakar
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2022-09-20 19:26 UTC (permalink / raw)
To: Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc,
Prabhakar Mahadev Lad
Just ignore my mail, As I realised IRQ property in each node will be a problem.
Cheers,
Biju
> -----Original Message-----
> From: Biju Das
> Sent: 20 September 2022 20:22
> To: Prabhakar <prabhakar.csengg@gmail.com>; Rob Herring
> <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>;
> Albert Ou <aou@eecs.berkeley.edu>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Conor
> Dooley <conor.dooley@microchip.com>
> Cc: Heiko Stuebner <heiko@sntech.de>; Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>; Atish Patra
> <atishp@rivosinc.com>; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> renesas-soc@vger.kernel.org; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> >
> > This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> > board DTSIs([0] and [1]).
>
> Just a question,
>
> Why can't we reuse SoC dtsi as well, as 90% of the SoC nodes are same?
>
> Split common stuff from arch/arm/boot/dts/renesas/r9a07g043.dtsi
>
> and add ARM specific CPU, IRQ to
> arch/arm/boot/dts/renesas/r9a07g043u.dtsi
>
> RISC-V specific CPU, IRQ to
> arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
>
> Both r9a07g043{u,f} dtsi will add common dtsi.
>
>
> Cheers,
> Biju
>
>
> >
> > As the RZ/G2UL SMARC EVK enables almost all the blocks supported by
> > the SoC and whereas for the RZ/Five SMARC EVK we will gradually be
> > enabling the blocks as a result we are adding the placeholder nodes
> to
> > avoid DTB compilation errors (currently we dont have support in DTC
> to
> > delete the reference nodes without actual nodes).
> >
> > [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> > ---
> > v3 -> v4
> > * Dropped status and reg-names properties
> > * Updated the commit message
> > * Note sbc node is not enabled in RZ/G2UL SMARC EVK but will be soon
> > enabled so added a placeholder for this too.
> >
> > v2 -> v3
> > * New patch
> > ---
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 150
> > +++++++++++++++++++++
> > 1 file changed, 150 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > index fb6733f3cc2b..d90d263b1b13 100644
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -13,6 +13,14 @@ / {
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + audio_clk1: audio1-clk {
> > + /* placeholder */
> > + };
> > +
> > + audio_clk2: audio2-clk {
> > + /* placeholder */
> > + };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -54,6 +62,19 @@ soc: soc {
> > #size-cells = <2>;
> > ranges;
> >
> > + ssi1: ssi@1004a000 {
> > + reg = <0 0x1004a000 0 0x400>;
> > + #sound-dai-cells = <0>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + spi1: spi@1004b000 {
> > + reg = <0 0x1004b000 0 0x400>;
> > +
> > + /* placeholder */
> > + };
> > +
> > scif0: serial@1004b800 {
> > compatible = "renesas,scif-r9a07g043",
> > "renesas,scif-r9a07g044";
> > @@ -73,6 +94,41 @@ scif0: serial@1004b800 {
> > status = "disabled";
> > };
> >
> > + canfd: can@10050000 {
> > + reg = <0 0x10050000 0 0x8000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + i2c0: i2c@10058000 {
> > + reg = <0 0x10058000 0 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + /* placeholder */
> > + };
> > +
> > + i2c1: i2c@10058400 {
> > + reg = <0 0x10058400 0 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + adc: adc@10059000 {
> > + reg = <0 0x10059000 0 0x400>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + sbc: spi@10060000 {
> > + reg = <0 0x10060000 0 0x10000>,
> > + <0 0x20000000 0 0x10000000>,
> > + <0 0x10070000 0 0x10000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > cpg: clock-controller@11010000 {
> > compatible = "renesas,r9a07g043-cpg";
> > reg = <0 0x11010000 0 0x10000>;
> > @@ -104,6 +160,82 @@ pinctrl: pinctrl@11030000 {
> > <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > };
> >
> > + sdhi0: mmc@11c00000 {
> > + reg = <0x0 0x11c00000 0 0x10000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + sdhi1: mmc@11c10000 {
> > + reg = <0x0 0x11c10000 0 0x10000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + eth0: ethernet@11c20000 {
> > + reg = <0 0x11c20000 0 0x10000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + eth1: ethernet@11c30000 {
> > + reg = <0 0x11c30000 0 0x10000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + phyrst: usbphy-ctrl@11c40000 {
> > + reg = <0 0x11c40000 0 0x10000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ohci0: usb@11c50000 {
> > + reg = <0 0x11c50000 0 0x100>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ohci1: usb@11c70000 {
> > + reg = <0 0x11c70000 0 0x100>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ehci0: usb@11c50100 {
> > + reg = <0 0x11c50100 0 0x100>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ehci1: usb@11c70100 {
> > + reg = <0 0x11c70100 0 0x100>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + usb2_phy0: usb-phy@11c50200 {
> > + reg = <0 0x11c50200 0 0x700>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + usb2_phy1: usb-phy@11c70200 {
> > + reg = <0 0x11c70200 0 0x700>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + hsusb: usb@11c60000 {
> > + reg = <0 0x11c60000 0 0x10000>;
> > +
> > + /* placeholder */
> > + };
> > +
> > plic: interrupt-controller@12c00000 {
> > compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
> > #interrupt-cells = <2>;
> > @@ -116,5 +248,23 @@ plic: interrupt-controller@12c00000 {
> > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> > };
> > +
> > + wdt0: watchdog@12800800 {
> > + reg = <0 0x12800800 0 0x400>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ostm1: timer@12801400 {
> > + reg = <0x0 0x12801400 0x0 0x400>;
> > +
> > + /* placeholder */
> > + };
> > +
> > + ostm2: timer@12801800 {
> > + reg = <0x0 0x12801800 0x0 0x400>;
> > +
> > + /* placeholder */
> > + };
> > };
> > };
> > --
> > 2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-20 19:26 ` Biju Das
@ 2022-09-20 20:51 ` Lad, Prabhakar
2022-09-21 5:22 ` Biju Das
0 siblings, 1 reply; 26+ messages in thread
From: Lad, Prabhakar @ 2022-09-20 20:51 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Biju,
On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
>
> Just ignore my mail, As I realised IRQ property in each node will be a problem.
>
Yes the IRQ numbers are different (offset of 32) along with the IRQ parent.
Refer this thread [0] where other SoC vendors have similar issues,
maybe in future when DTC becomes more clever we can use single SoC
DTSI for both.
[0] https://lore.kernel.org/lkml/CAMuHMdUMM9H4jLJ8-zOz9SXoqmK-s4zRWzGCsU8jt_sDgY1h+Q@mail.gmail.com/
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-20 20:51 ` Lad, Prabhakar
@ 2022-09-21 5:22 ` Biju Das
2022-09-21 7:49 ` Geert Uytterhoeven
0 siblings, 1 reply; 26+ messages in thread
From: Biju Das @ 2022-09-21 5:22 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Prabhakar,
> Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> nodes
>
> Hi Biju,
>
> On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> >
> > Just ignore my mail, As I realised IRQ property in each node will be
> a problem.
> >
> Yes the IRQ numbers are different (offset of 32) along with the IRQ
> parent.
>
> Refer this thread [0] where other SoC vendors have similar issues,
> maybe in future when DTC becomes more clever we can use single SoC
> DTSI for both.
Not sure, May be the macro suggestion mentioned in that thread will work for us??
As it is just only the interrupt properties that differ which is
handled in macro. A Generic macro in common dtsi which is
expanded in RISCV or arm64 specific dtsi to get proper one??
Cheers,
Biju
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes
2022-09-21 5:22 ` Biju Das
@ 2022-09-21 7:49 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2022-09-21 7:49 UTC (permalink / raw)
To: Biju Das
Cc: Lad, Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley, Heiko Stuebner, Heinrich Schuchardt, Atish Patra,
devicetree, linux-kernel, linux-riscv, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Biju,
On Wed, Sep 21, 2022 at 7:22 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder
> > nodes
> > On Tue, Sep 20, 2022 at 8:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Just ignore my mail, As I realised IRQ property in each node will be
> > a problem.
> > >
> > Yes the IRQ numbers are different (offset of 32) along with the IRQ
> > parent.
> >
> > Refer this thread [0] where other SoC vendors have similar issues,
> > maybe in future when DTC becomes more clever we can use single SoC
> > DTSI for both.
>
> Not sure, May be the macro suggestion mentioned in that thread will work for us??
> As it is just only the interrupt properties that differ which is
> handled in macro. A Generic macro in common dtsi which is
> expanded in RISCV or arm64 specific dtsi to get proper one??
I brought it up with the DT people in a separate thread[1].
Please continue the discussion there.
Thanks!
[1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@mail.gmail.com
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (6 preceding siblings ...)
2022-09-20 18:49 ` [PATCH v4 07/10] riscv: dts: r9a07g043: Add placeholder nodes Prabhakar
@ 2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
` (2 subsequent siblings)
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
As we are reusing the RZ/G2UL SMARC SoM [0] and carrier [1] board DTSIs
which enables almost all the blocks supported by the RZ/G2UL SoC and
whereas on RZ/Five SoC we will be gradually adding the blocks hence the
aliases for ETH and I2C are deleted as support for these blocks is not
yet enabled on RZ/Five SoC.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3 -> v4
* Dropped deleting place holder nodes
* Updated SW1 settings comment
* Update commit message
v2 -> v3
* Dropped RB tags from Conor and Geert
* Now re-using the SoM and carrier board DTS/I from RZ/G2UL
v1 -> v2
* New patch
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 ++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++++++++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 +++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +++++++++++
5 files changed, 64 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..487d0d5e6d2e
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..d8168eb920ab
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..6f44a6946897
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (7 preceding siblings ...)
2022-09-20 18:49 ` [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
@ 2022-09-20 18:49 ` Prabhakar
2022-09-20 18:49 ` [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-09-20 19:20 ` [PATCH v4 00/10] Add support for " Conor Dooley
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3 -> v4
* Included RB tag from Geert
v2 -> v3
* Merged as part of ARM
v1 -> v2
* New patch
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 48c5a152f743..fbf507cd3f41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2671,7 +2671,7 @@ F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
-ARM/RENESAS ARCHITECTURE
+ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <geert+renesas@glider.be>
M: Magnus Damm <magnus.damm@gmail.com>
L: linux-renesas-soc@vger.kernel.org
@@ -2692,6 +2692,7 @@ F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: arch/arm64/boot/dts/renesas/
+F: arch/riscv/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (8 preceding siblings ...)
2022-09-20 18:49 ` [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
@ 2022-09-20 18:49 ` Prabhakar
2022-09-20 19:20 ` [PATCH v4 00/10] Add support for " Conor Dooley
10 siblings, 0 replies; 26+ messages in thread
From: Prabhakar @ 2022-09-20 18:49 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley
Cc: Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Prabhakar,
Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.
Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
tags with this change)
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tags
* Updated commit description
v1 -> v2
* New patch
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v4 00/10] Add support for Renesas RZ/Five SoC
2022-09-20 18:48 [PATCH v4 00/10] Add support for Renesas RZ/Five SoC Prabhakar
` (9 preceding siblings ...)
2022-09-20 18:49 ` [PATCH v4 10/10] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
@ 2022-09-20 19:20 ` Conor Dooley
2022-09-20 19:24 ` Geert Uytterhoeven
10 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2022-09-20 19:20 UTC (permalink / raw)
To: Prabhakar
Cc: Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Geert Uytterhoeven, Magnus Damm, Conor Dooley,
Heiko Stuebner, Heinrich Schuchardt, Atish Patra, devicetree,
linux-kernel, linux-riscv, linux-renesas-soc, Biju Das,
Lad Prabhakar
Hey Prabhakar,
On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC and updates the bindings for the same. Below is the list
> of IP blocks added in the initial SoC DTSI which can be used to boot via
> initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
Ran into one complaint from dtbs_check:
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
Other than that which should be a trivial fix the whole lot looks good
to me...
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below (which are already in -next apart from the last one):
> --------------------------------------------------
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220914134211.199631-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220915165256.352843-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220919104606.96553-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> v3 -> v4:
> -------
> * Rebased patches on -next
> * Included RB tags
> * Fixed review comments pointed by Conor and Geert
>
> v3: https://lore.kernel.org/lkml/20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v2: https://lore.kernel.org/all/20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> v1: https://lore.kernel.org/lkml/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
> / # uname -ra
> Linux (none) 6.0.0-rc6-next-20220920-00025-gc002c40ce550-dirty #136 SMP Tue Sep 20 13:47:31 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 33 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 919 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 44106 RISC-V INTC 5 Edge riscv-timer
> 6: 62 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882308 kB
> MemFree: 861440 kB
> MemAvailable: 859188 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 84 kB
> Active(anon): 0 kB
> Inactive(anon): 84 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 120 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6732 kB
> Slab: 12088 kB
> SReclaimable: 6732 kB
> SUnreclaim: 5356 kB
> KernelStack: 636 kB
> PageTables: 32 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441152 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 840 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
>
> -------------------
>
>
> Lad Prabhakar (10):
> dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: r9a07g043: Add placeholder nodes
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V architecture
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 +-
> .../{arm => soc/renesas}/renesas.yaml | 5 +-
> MAINTAINERS | 4 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 270 ++++++++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 ++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +
> arch/riscv/configs/defconfig | 3 +
> 11 files changed, 353 insertions(+), 9 deletions(-)
> rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (98%)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v4 00/10] Add support for Renesas RZ/Five SoC
2022-09-20 19:20 ` [PATCH v4 00/10] Add support for " Conor Dooley
@ 2022-09-20 19:24 ` Geert Uytterhoeven
2022-09-20 19:37 ` Conor Dooley
0 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2022-09-20 19:24 UTC (permalink / raw)
To: Conor Dooley
Cc: Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley, Heiko Stuebner, Heinrich Schuchardt, Atish Patra,
devicetree, linux-kernel, linux-riscv, linux-renesas-soc,
Biju Das, Lad Prabhakar
Hi Conor,
On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <conor@kernel.org> wrote:
> On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > entry-class social infrastructure gateway control and industrial gateway
> > control.
> >
> > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
>
> Ran into one complaint from dtbs_check:
> arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
>
> Other than that which should be a trivial fix the whole lot looks good
> to me...
That's due to the placeholders...
Currently it is not yet a requirement that "make dtbs_check" is warning-free.
I'm wondering how we have to handle new SoCs with existing boards in
the future. Probably just more properties in the placeholders...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v4 00/10] Add support for Renesas RZ/Five SoC
2022-09-20 19:24 ` Geert Uytterhoeven
@ 2022-09-20 19:37 ` Conor Dooley
2022-09-20 20:43 ` Lad, Prabhakar
0 siblings, 1 reply; 26+ messages in thread
From: Conor Dooley @ 2022-09-20 19:37 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Prabhakar, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Geert Uytterhoeven, Magnus Damm,
Conor Dooley, Heiko Stuebner, Heinrich Schuchardt, Atish Patra,
devicetree, linux-kernel, linux-riscv, linux-renesas-soc,
Biju Das, Lad Prabhakar
On Tue, Sep 20, 2022 at 09:24:05PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <conor@kernel.org> wrote:
> > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > entry-class social infrastructure gateway control and industrial gateway
> > > control.
> > >
> > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > > initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - CPG
> > > - PINCTRL
> > > - PLIC
> > > - SCIF0
> > > - SYSC
> >
> > Ran into one complaint from dtbs_check:
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> >
> > Other than that which should be a trivial fix the whole lot looks good
> > to me...
>
> That's due to the placeholders...
Right, but #phy-cells will be added into the usb-phys once you (plural)
figure out how to integrate with the existing CMO stuff?
> Currently it is not yet a requirement that "make dtbs_check" is warning-free.
I was really hoping that it could be a requirement for 6.1 onwards. I've
managed to clear all of the other ones from arch/riscv.
> I'm wondering how we have to handle new SoCs with existing boards in
> the future. Probably just more properties in the placeholders...
New SoCs to existing boards is less of a problem then new CPUs to
existing SoCs from what I can see...
I know we just discussed it earlier today, but is it possible to make
these particular placeholders more complete so that dtbs_check shuts up
about them?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4 00/10] Add support for Renesas RZ/Five SoC
2022-09-20 19:37 ` Conor Dooley
@ 2022-09-20 20:43 ` Lad, Prabhakar
0 siblings, 0 replies; 26+ messages in thread
From: Lad, Prabhakar @ 2022-09-20 20:43 UTC (permalink / raw)
To: Conor Dooley
Cc: Geert Uytterhoeven, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Geert Uytterhoeven,
Magnus Damm, Conor Dooley, Heiko Stuebner, Heinrich Schuchardt,
Atish Patra, devicetree, linux-kernel, linux-riscv,
linux-renesas-soc, Biju Das, Lad Prabhakar
Hi Conor,
Thank you for the review.
On Tue, Sep 20, 2022 at 8:38 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Sep 20, 2022 at 09:24:05PM +0200, Geert Uytterhoeven wrote:
> > Hi Conor,
> >
> > On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <conor@kernel.org> wrote:
> > > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > entry-class social infrastructure gateway control and industrial gateway
> > > > control.
> > > >
> > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > > > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > > > initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - CPG
> > > > - PINCTRL
> > > > - PLIC
> > > > - SCIF0
> > > > - SYSC
> > >
> > > Ran into one complaint from dtbs_check:
> > > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> > > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> > > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > >
> > > Other than that which should be a trivial fix the whole lot looks good
> > > to me...
> >
> > That's due to the placeholders...
>
> Right, but #phy-cells will be added into the usb-phys once you (plural)
> figure out how to integrate with the existing CMO stuff?
>
Yes indeed.
> > Currently it is not yet a requirement that "make dtbs_check" is warning-free.
>
> I was really hoping that it could be a requirement for 6.1 onwards. I've
> managed to clear all of the other ones from arch/riscv.
>
Maybe i'll fix it and respin the series (along with the Kconfig.socs sorted).
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 26+ messages in thread