* [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
@ 2019-02-07 8:31 Biju Das
2019-02-07 8:31 ` [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support Biju Das
2019-02-07 10:13 ` [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Geert Uytterhoeven
0 siblings, 2 replies; 6+ messages in thread
From: Biju Das @ 2019-02-07 8:31 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
mapping for pciec0 node. Also declare pcie bus clock, since it is
generated on the CAT874 main board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
This patch is tested against renesas-dev
---
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 477a56b..96ee0d2c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -56,6 +56,15 @@
clock-frequency = <48000000>;
};
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
&pfc {
scif2_pins: scif2 {
groups = "scif2_data_a";
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support
2019-02-07 8:31 [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Biju Das
@ 2019-02-07 8:31 ` Biju Das
2019-02-07 10:13 ` Geert Uytterhoeven
2019-02-07 10:13 ` [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Geert Uytterhoeven
1 sibling, 1 reply; 6+ messages in thread
From: Biju Das @ 2019-02-07 8:31 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Biju Das, Simon Horman, Magnus Damm, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
This patch enables PCIEC0 PCI express controller on the sub board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
This patch is tested against renesas-dev
---
arch/arm64/boot/dts/renesas/cat875.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index 805ffa7..14db667 100644
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -30,6 +30,10 @@
};
};
+&pciec0 {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
mux {
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support
2019-02-07 8:31 ` [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support Biju Das
@ 2019-02-07 10:13 ` Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman
0 siblings, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2019-02-07 10:13 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Feb 7, 2019 at 9:37 AM Biju Das <biju.das@bp.renesas.com> wrote:
> This patch enables PCIEC0 PCI express controller on the sub board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support
2019-02-07 10:13 ` Geert Uytterhoeven
@ 2019-02-07 10:43 ` Simon Horman
0 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2019-02-07 10:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Feb 07, 2019 at 11:13:21AM +0100, Geert Uytterhoeven wrote:
> On Thu, Feb 7, 2019 at 9:37 AM Biju Das <biju.das@bp.renesas.com> wrote:
> > This patch enables PCIEC0 PCI express controller on the sub board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v5.1.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
2019-02-07 8:31 [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Biju Das
2019-02-07 8:31 ` [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support Biju Das
@ 2019-02-07 10:13 ` Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman
1 sibling, 1 reply; 6+ messages in thread
From: Geert Uytterhoeven @ 2019-02-07 10:13 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Feb 7, 2019 at 9:37 AM Biju Das <biju.das@bp.renesas.com> wrote:
> Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
> mapping for pciec0 node. Also declare pcie bus clock, since it is
> generated on the CAT874 main board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
2019-02-07 10:13 ` [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Geert Uytterhoeven
@ 2019-02-07 10:43 ` Simon Horman
0 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2019-02-07 10:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Fabrizio Castro
On Thu, Feb 07, 2019 at 11:13:03AM +0100, Geert Uytterhoeven wrote:
> On Thu, Feb 7, 2019 at 9:37 AM Biju Das <biju.das@bp.renesas.com> wrote:
> > Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
> > mapping for pciec0 node. Also declare pcie bus clock, since it is
> > generated on the CAT874 main board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v5.1.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-02-07 10:43 UTC | newest]
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2019-02-07 8:31 [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Biju Das
2019-02-07 8:31 ` [PATCH 2/2] arm64: dts: renesas: cat875: Enable PCIe support Biju Das
2019-02-07 10:13 ` Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman
2019-02-07 10:13 ` [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Geert Uytterhoeven
2019-02-07 10:43 ` Simon Horman
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