From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor.dooley@microchip.com>,
Samuel Holland <samuel@sholland.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
DT <devicetree@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts
Date: Tue, 25 Oct 2022 14:40:45 +0200 [thread overview]
Message-ID: <CAMuHMdVfExBuXNiRBaPRqaX9AvDprTHec7+1K-7Un6gDf6VWJA@mail.gmail.com> (raw)
In-Reply-To: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Thu, Sep 29, 2022 at 7:24 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
> so that this can be shared with the RZ/Five SoC.
>
> Implementation is based on the discussion [0] where I have used option#2.
>
> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
> (r9a07g043F.dtsi)
Thanks for your series!
> r9a07g043f.dtsi will look something like below:
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
Originally, when I assumed incorrectly that dtc does not support
arithmetic, I used "nr" and "na" in the macro I proposed to mean RISC-V
("r") resp. ARM ("a") interrupt number. Apparently the names stuck,
although the second parameter now has a completely different meaning ;-)
However, as the NCEPLIC does support interrupt flags, unlike the SiFive
PLIC, there is no need to have the flags parameter in the macro.
Moreover, it looks like the SOC_PERIPHERAL_IRQ_NUMBER()
intermediate is not needed, so you can just write:
#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> #include <arm64/renesas/r9a07g043.dtsi>
>
> / {
> ...
> ...
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
prev parent reply other threads:[~2022-10-25 12:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 17:23 [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts Prabhakar
2022-09-29 17:23 ` [RFC PATCH 1/2] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Prabhakar
2022-09-29 17:23 ` [RFC PATCH 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Prabhakar
2022-10-10 9:41 ` [RFC PATCH 0/2] RZ/G2UL separate out " Lad, Prabhakar
2022-10-12 15:38 ` Krzysztof Kozlowski
2022-10-12 19:00 ` Lad, Prabhakar
2022-10-25 12:40 ` Geert Uytterhoeven [this message]
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