From: Paul Walmsley <paul.walmsley@sifive.com>
To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Stephen Boyd <sboyd@kernel.org>,
"Wesley W . Terpstra" <wesley@sifive.com>,
Michael Turquette <mturquette@baylibre.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, Megan Wachs <megan@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: [PATCH v2 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls
Date: Sat, 20 Oct 2018 06:50:21 -0700 [thread overview]
Message-ID: <20181020135024.28573-1-paul.walmsley@sifive.com> (raw)
Message-ID: <20181020135021.6LpxFV740NPITMG8g0_KHLf0Dae00KtWr_3lRglL8GQ@z> (raw)
Add a driver for the SiFive FU540 PRCI IP block, which handles clock and
some device reset control for the SiFive FU540 chip. Also add a driver-
independent library for the Analog Bits Wide-Range PLL (WRPLL), used by
the PRCI driver to monitor and control the WRPLL instances on the FU540
chip.
It's been a long time since I've worked on Linux clock code, so Mike &
Stephen, I'd appreciate a close look at the PRCI driver to make sure
what it's doing makes sense.
Boot-tested on a SiFive HiFive Unleashed board. COREPLL rate changes
and notification were also tested on the same board.
This second version corrects the DT binding documentation patch; an
out-of-date version of that patch was sent with the first version.
This patch series is also available at:
https://github.com/sifive/riscv-linux/tree/dev/paulw/prci-v4.19-rc7
Paul Walmsley (3):
clk: analogbits: add Wide-Range PLL library
dt-bindings: clk: add documentation for the SiFive PRCI driver
clk: sifive: add a driver for the SiFive FU540 PRCI IP block
.../bindings/clock/sifive/fu540-prci.txt | 43 ++
MAINTAINERS | 6 +
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 2 +
drivers/clk/analogbits/Kconfig | 3 +
drivers/clk/analogbits/Makefile | 2 +
drivers/clk/analogbits/wrpll-cln28hpc.c | 387 +++++++++++
drivers/clk/sifive/Kconfig | 18 +
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu540-prci.c | 634 ++++++++++++++++++
include/linux/clk/analogbits-wrpll-cln28hpc.h | 99 +++
include/linux/clk/sifive-fu540-prci.h | 27 +
12 files changed, 1224 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
create mode 100644 drivers/clk/analogbits/Kconfig
create mode 100644 drivers/clk/analogbits/Makefile
create mode 100644 drivers/clk/analogbits/wrpll-cln28hpc.c
create mode 100644 drivers/clk/sifive/Kconfig
create mode 100644 drivers/clk/sifive/Makefile
create mode 100644 drivers/clk/sifive/fu540-prci.c
create mode 100644 include/linux/clk/analogbits-wrpll-cln28hpc.h
create mode 100644 include/linux/clk/sifive-fu540-prci.h
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Wesley W. Terpstra <wesley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Megan Wachs <megan@sifive.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
--
2.19.1
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next reply other threads:[~2018-10-20 13:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-20 13:50 Paul Walmsley [this message]
2018-10-20 13:50 ` [PATCH v2 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls Paul Walmsley
2018-10-20 13:50 ` [PATCH v2 2/3] dt-bindings: clk: add documentation for the SiFive PRCI driver Paul Walmsley
2018-10-20 13:50 ` Paul Walmsley
2018-10-24 18:47 ` Rob Herring
2018-10-24 18:47 ` Rob Herring
2018-11-16 23:18 ` Paul Walmsley
2018-11-16 23:18 ` Paul Walmsley
2018-11-06 17:33 ` Stephen Boyd
2018-11-06 17:33 ` Stephen Boyd
2018-11-07 2:00 ` Paul Walmsley
2018-11-07 2:00 ` Paul Walmsley
2018-10-20 13:50 ` [PATCH v2 3/3] clk: sifive: add a driver for the SiFive FU540 PRCI IP block Paul Walmsley
2018-10-20 13:50 ` Paul Walmsley
2018-11-21 16:35 ` Stephen Boyd
2018-11-21 16:35 ` Stephen Boyd
2018-11-27 23:24 ` Paul Walmsley
2018-11-27 23:24 ` Paul Walmsley
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