From: Anup Patel <anup@brainfault.org>
To: Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present
Date: Fri, 30 Nov 2018 13:32:05 +0530 [thread overview]
Message-ID: <20181130080207.20505-5-anup@brainfault.org> (raw)
In-Reply-To: <20181130080207.20505-1-anup@brainfault.org>
We have two enteries (one for M-mode and another for S-mode) in the
interrupts-extended DT property of PLIC DT node for each HART. It is
expected that firmware/bootloader will set M-mode HWIRQ line of each
HART to 0xffffffff (i.e. -1) in interrupts-extended DT property
because Linux runs in S-mode only.
If firmware/bootloader is buggy then it will not correctly update
interrupts-extended DT property which might result in a plic_handler
configured twice. This patch adds a warning in plic_init() if a
plic_handler is already marked present. This warning provides us
a hint about incorrectly updated interrupts-extended DT property.
Signed-off-by: Anup Patel <anup@brainfault.org>
---
drivers/irqchip/irq-sifive-plic.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index d4433399eb89..3d4f205f8abe 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -234,6 +234,11 @@ static int __init plic_init(struct device_node *node,
cpu = riscv_hartid_to_cpuid(hartid);
handler = per_cpu_ptr(&plic_handlers, cpu);
+ if (handler->present) {
+ pr_warn("handler not available for context %d.\n", i);
+ continue;
+ }
+
handler->present = true;
handler->hart_base =
plic.regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
--
2.17.1
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next prev parent reply other threads:[~2018-11-30 8:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-30 8:02 [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel
2018-11-30 8:02 ` [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-12-17 18:25 ` Christoph Hellwig
2018-12-18 8:30 ` Anup Patel
2018-11-30 8:02 ` [PATCH v3 2/6] irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details Anup Patel
2018-12-17 18:24 ` Christoph Hellwig
2018-12-18 8:25 ` Anup Patel
2018-11-30 8:02 ` [PATCH v3 3/6] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel
2018-12-17 18:27 ` Christoph Hellwig
2018-12-18 8:50 ` Anup Patel
2018-12-19 16:28 ` Christoph Hellwig
2018-12-27 5:27 ` Anup Patel
2018-11-30 8:02 ` Anup Patel [this message]
2018-12-17 18:28 ` [PATCH v3 4/6] irqchip: sifive-plic: Add warning in plic_init() if handler already present Christoph Hellwig
2018-12-18 8:36 ` Anup Patel
2018-11-30 8:02 ` [PATCH v3 5/6] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-11-30 8:02 ` [PATCH v3 6/6] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-12-17 18:32 ` Christoph Hellwig
2018-12-18 10:32 ` Anup Patel
2018-12-17 9:37 ` [PATCH v3 0/6] IRQ affinity support in PLIC driver Anup Patel
2018-12-20 20:40 ` Palmer Dabbelt
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