From: Rob Herring <robh@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed
Date: Thu, 20 Dec 2018 15:31:20 -0600 [thread overview]
Message-ID: <20181220212618.GA27359@bogus> (raw)
In-Reply-To: <20181215052154.24347-8-paul.walmsley@sifive.com>
On Fri, Dec 14, 2018 at 09:21:54PM -0800, Paul Walmsley wrote:
> Add initial board data for the SiFive HiFive Unleashed A00.
>
> Currently the data populated in this DT file describes the board
> DRAM configuration and the external clock sources that supply the
> PRCI.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
> arch/riscv/boot/dts/Makefile | 2 +
> arch/riscv/boot/dts/sifive/Makefile | 4 ++
> .../dts/sifive/hifive-unleashed-a00-fu540.dts | 39 +++++++++++++++++++
> 3 files changed, 45 insertions(+)
> create mode 100644 arch/riscv/boot/dts/Makefile
> create mode 100644 arch/riscv/boot/dts/sifive/Makefile
> create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> new file mode 100644
> index 000000000000..dcc3ada78455
> --- /dev/null
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile
> new file mode 100644
> index 000000000000..e120ccf5649c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00-fu540.dtb
> +
> +
> diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> new file mode 100644
> index 000000000000..0c6afabe69e3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: Apache-2.0
> +// SPDX-License-Identifier: GPL-2.0-or-later
This should be a single line with: (Apache-2.0 OR GPL-2.0+)
> +/* Copyright (c) 2018 SiFive, Inc */
> +/* See the file LICENSE for further information */
> +
> +/dts-v1/;
> +
> +#include "fu540-c000.dtsi"
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SiFive HiFive Unleashed A00 (FU540-C000)"
> + compatible = "sifive,hifive-unleashed-a00-fu540",
> + "sifive,hifive-unleashed-fu540";
SoC compatible should be here too.
> +
> + chosen {
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x1f 0x80000000>;
> + };
> +
> + soc {
> + hfclk: hfclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <33333333>;
> + clock-output-names = "hfclk";
> + };
> + rtcclk: rtcclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <1000000>;
> + clock-output-names = "rtcclk";
> + };
Are these the clock inputs to the SoC or dummy clocks until you write a
proper clock driver? If the former, they should be at the top level.
Rob
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next prev parent reply other threads:[~2018-12-20 21:31 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-15 5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
2018-12-15 5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2018-12-15 5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley
2018-12-20 20:57 ` Rob Herring
2018-12-15 5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley
2018-12-20 21:01 ` Rob Herring
2019-01-04 22:46 ` Palmer Dabbelt
2019-01-05 1:10 ` Rob Herring
2018-12-15 5:21 ` [PATCH 4/7] dt-bindings: riscv: cpus: add U54 " Paul Walmsley
2018-12-15 5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2018-12-16 3:12 ` kbuild test robot
2019-01-21 14:10 ` Johan Hovold
2018-12-15 5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley
2018-12-20 21:04 ` Rob Herring
2018-12-15 5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2018-12-20 21:31 ` Rob Herring [this message]
2019-04-06 23:14 ` Paul Walmsley
2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
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