From: Paul Walmsley <paul.walmsley@sifive.com>
To: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed
Date: Sat, 6 Apr 2019 16:14:32 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1904061612310.18279@viisi.sifive.com> (raw)
In-Reply-To: <20181220212618.GA27359@bogus>
On Thu, 20 Dec 2018, Rob Herring wrote:
> On Fri, Dec 14, 2018 at 09:21:54PM -0800, Paul Walmsley wrote:
> > Add initial board data for the SiFive HiFive Unleashed A00.
> >
> > Currently the data populated in this DT file describes the board
> > DRAM configuration and the external clock sources that supply the
> > PRCI.
...
> > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> > new file mode 100644
> > index 000000000000..0c6afabe69e3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-fu540.dts
> > @@ -0,0 +1,39 @@
> > +// SPDX-License-Identifier: Apache-2.0
> > +// SPDX-License-Identifier: GPL-2.0-or-later
>
> This should be a single line with: (Apache-2.0 OR GPL-2.0+)
Done.
> > + model = "SiFive HiFive Unleashed A00 (FU540-C000)"
> > + compatible = "sifive,hifive-unleashed-a00-fu540",
> > + "sifive,hifive-unleashed-fu540";
>
> SoC compatible should be here too.
Done.
> > + soc {
> > + hfclk: hfclk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <33333333>;
> > + clock-output-names = "hfclk";
> > + };
> > + rtcclk: rtcclk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <1000000>;
> > + clock-output-names = "rtcclk";
> > + };
>
> Are these the clock inputs to the SoC or dummy clocks until you write a
> proper clock driver? If the former, they should be at the top level.
Done.
Thanks for your comments; Will send an updated patch set.
- Paul
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next prev parent reply other threads:[~2019-04-06 23:14 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-15 5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
2018-12-15 5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2018-12-15 5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley
2018-12-20 20:57 ` Rob Herring
2018-12-15 5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley
2018-12-20 21:01 ` Rob Herring
2019-01-04 22:46 ` Palmer Dabbelt
2019-01-05 1:10 ` Rob Herring
2018-12-15 5:21 ` [PATCH 4/7] dt-bindings: riscv: cpus: add U54 " Paul Walmsley
2018-12-15 5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2018-12-16 3:12 ` kbuild test robot
2019-01-21 14:10 ` Johan Hovold
2018-12-15 5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley
2018-12-20 21:04 ` Rob Herring
2018-12-15 5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2018-12-20 21:31 ` Rob Herring
2019-04-06 23:14 ` Paul Walmsley [this message]
2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
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