From: Christoph Hellwig <hch@infradead.org>
To: Gary Guo <gary@garyguo.net>
Cc: Christoph Hellwig <hch@infradead.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v4 4/5] riscv: rewrite tlb flush for performance
Date: Thu, 28 Mar 2019 09:55:31 -0700 [thread overview]
Message-ID: <20190328165531.GA10231@infradead.org> (raw)
In-Reply-To: <ad35a3db-cfe2-f37f-b520-fc67091e8e9e@garyguo.net>
On Thu, Mar 28, 2019 at 04:39:53PM +0000, Gary Guo wrote:
> > I'd rather keep it simple for now. For ASID support I suspect you'll
> > only need it to get the asid from the mm_struct pointer to by the
> > vma, right? I'd rather pass the asid directly in that case.
> >
>
> Yes, just takes it from mm_struct. But the key point is to keep it
> similar to the local_flush_tlb_page.
And I'd much rather not pass unused argument that also require
duplicating the inline assembly code.
> > And I'd still like an answer for my sectond question above - what
> > were the good values for say the sifive u54 and qemu in your tests?
> >
> QEMU currently treats all SFENCE.VMA as global. Technically the QEMU's
> implementation can be modified to do page-level flush instead but the
> performance will not differ, as the dominating factor is resetting jump
> cache.
>
> I don't have a SiFive board so I can't tell what's a good value for that.
>
> On a hypothetical platform that I am working at (simulation only) we can
> benefit even when setting it to 511 (max allowed, as if value >=512 we
> don't know if a non-leaf entry is changed, in which case spec mandates a
> full flush).
>
> So this really depends on the platform.
Ok, so before moving on we really should figure out a good way for
the currently only support (well mostly supported) hardware platform
and figure out a way to pass that through DT.
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next prev parent reply other threads:[~2019-03-28 16:55 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 0:41 [PATCH v4 0/5] TLB/I$ flush cleanups and improvements Gary Guo
2019-03-27 0:41 ` [PATCH v4 1/5] riscv: move flush_icache_{all,mm} to cacheflush.c Gary Guo
2019-03-27 7:06 ` Christoph Hellwig
2019-03-28 6:45 ` Anup Patel
2019-03-27 0:41 ` [PATCH v4 3/5] riscv: fix sbi_remote_sfence_vma{,_asid} Gary Guo
2019-03-27 7:08 ` Christoph Hellwig
2019-03-28 6:47 ` Anup Patel
2019-03-27 0:41 ` [PATCH v4 4/5] riscv: rewrite tlb flush for performance Gary Guo
2019-03-27 7:25 ` Christoph Hellwig
2019-03-27 13:56 ` Gary Guo
2019-03-28 16:17 ` Christoph Hellwig
2019-03-28 16:39 ` Gary Guo
2019-03-28 16:55 ` Christoph Hellwig [this message]
2019-03-27 0:41 ` [PATCH v4 2/5] riscv: move switch_mm to its own file Gary Guo
2019-03-27 7:08 ` Christoph Hellwig
2019-03-27 7:18 ` Christoph Hellwig
2019-03-28 6:47 ` Anup Patel
2019-03-27 0:41 ` [PATCH v4 5/5] riscv: implement IPI-based remote TLB shootdown Gary Guo
2019-03-27 7:31 ` Christoph Hellwig
2019-03-27 14:03 ` Gary Guo
2019-03-28 16:36 ` Christoph Hellwig
2019-03-28 16:47 ` Gary Guo
2019-03-28 16:57 ` Christoph Hellwig
2019-03-28 6:50 ` Anup Patel
2019-04-10 7:04 ` [PATCH v4 0/5] TLB/I$ flush cleanups and improvements Christoph Hellwig
2019-04-10 9:01 ` Anup Patel
2019-04-10 10:11 ` Christoph Hellwig
2019-04-10 10:22 ` Anup Patel
2019-04-11 1:24 ` Atish Patra
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