From: Gary Guo <gary@garyguo.net>
To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>
Cc: Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Anup Patel <Anup.Patel@wdc.com>, Gary Guo <gary@garyguo.net>
Subject: [PATCH v4 5/5] riscv: implement IPI-based remote TLB shootdown
Date: Wed, 27 Mar 2019 00:41:30 +0000 [thread overview]
Message-ID: <d1c980f2e49192c7cb2ddd4f3e4af577d1eaf539.1553647082.git.gary@garyguo.net> (raw)
In-Reply-To: <cover.1553647082.git.gary@garyguo.net>
From: Gary Guo <gary@garyguo.net>
This patch implements IPI-based remote TLB shootdown, which is useful
at this stage for testing because BBL/OpenSBI ignores operands of
sbi_remote_sfence_vma_asid and always perform a global TLB flush.
The SBI-based remote TLB shootdown can still be opt-in using boot
cmdline "tlbi_method=sbi".
Signed-off-by: Gary Guo <gary@garyguo.net>
Tested-by: Atish Patra <atish.patra@wdc.com>
---
.../admin-guide/kernel-parameters.txt | 5 +
arch/riscv/mm/tlbflush.c | 99 +++++++++++++++++--
2 files changed, 98 insertions(+), 6 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 7a60edef09d2..afd34fa1db91 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4552,6 +4552,11 @@
flushed.
See arch/riscv/mm/tlbflush.c
+ tlbi_method= [RV]
+ Format: { "sbi", "ipi" }
+ Default: "ipi"
+ Specify the method used to perform remote TLB shootdown.
+
tmem [KNL,XEN]
Enable the Transcendent memory driver if built-in.
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 33083f48a936..ceee76f14a0a 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -72,19 +72,106 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
#ifdef CONFIG_SMP
+/*
+ * SBI has interfaces for remote TLB shootdown. If there is no hardware
+ * remote TLB shootdown support, SBI perform IPIs itself instead. Some SBI
+ * implementations may also ignore ASID and address ranges provided and do a
+ * full TLB flush instead. In these cases we might want to do IPIs ourselves.
+ *
+ * This parameter allows the approach (IPI/SBI) to be specified using boot
+ * cmdline.
+ */
+static bool tlbi_ipi = true;
+
+static int __init setup_tlbi_method(char *str)
+{
+ if (strcmp(str, "ipi") == 0)
+ tlbi_ipi = true;
+ else if (strcmp(str, "sbi") == 0)
+ tlbi_ipi = false;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+early_param("tlbi_method", setup_tlbi_method);
+
+
+struct tlbi {
+ unsigned long start;
+ unsigned long size;
+ unsigned long asid;
+};
+
+static void ipi_remote_sfence_vma(void *info)
+{
+ struct tlbi *data = info;
+ unsigned long start = data->start;
+ unsigned long size = data->size;
+ unsigned long i;
+
+ if (size == SFENCE_VMA_FLUSH_ALL) {
+ local_flush_tlb_all();
+ }
+
+ for (i = 0; i < size; i += PAGE_SIZE) {
+ __asm__ __volatile__ ("sfence.vma %0"
+ : : "r" (start + i)
+ : "memory");
+ }
+}
+
+static void ipi_remote_sfence_vma_asid(void *info)
+{
+ struct tlbi *data = info;
+ unsigned long asid = data->asid;
+ unsigned long start = data->start;
+ unsigned long size = data->size;
+ unsigned long i;
+
+ if (size == SFENCE_VMA_FLUSH_ALL) {
+ __asm__ __volatile__ ("sfence.vma x0, %0"
+ : : "r" (asid)
+ : "memory");
+ return;
+ }
+
+ for (i = 0; i < size; i += PAGE_SIZE) {
+ __asm__ __volatile__ ("sfence.vma %0, %1"
+ : : "r" (start + i), "r" (asid)
+ : "memory");
+ }
+}
+
static void remote_sfence_vma(unsigned long start, unsigned long size)
{
- sbi_remote_sfence_vma(NULL, start, size);
+ if (tlbi_ipi) {
+ struct tlbi info = {
+ .start = start,
+ .size = size,
+ };
+ on_each_cpu(ipi_remote_sfence_vma, &info, 1);
+ } else
+ sbi_remote_sfence_vma(NULL, start, size);
}
static void remote_sfence_vma_asid(cpumask_t *mask, unsigned long start,
unsigned long size, unsigned long asid)
{
- cpumask_t hmask;
-
- cpumask_clear(&hmask);
- riscv_cpuid_to_hartid_mask(mask, &hmask);
- sbi_remote_sfence_vma_asid(hmask.bits, start, size, asid);
+ if (tlbi_ipi) {
+ struct tlbi info = {
+ .start = start,
+ .size = size,
+ .asid = asid,
+ };
+ on_each_cpu_mask(mask, ipi_remote_sfence_vma_asid, &info, 1);
+ } else {
+ cpumask_t hmask;
+
+ cpumask_clear(&hmask);
+ riscv_cpuid_to_hartid_mask(mask, &hmask);
+ sbi_remote_sfence_vma_asid(hmask.bits, start, size, asid);
+ }
}
--
2.17.1
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next prev parent reply other threads:[~2019-03-27 0:41 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 0:41 [PATCH v4 0/5] TLB/I$ flush cleanups and improvements Gary Guo
2019-03-27 0:41 ` [PATCH v4 1/5] riscv: move flush_icache_{all,mm} to cacheflush.c Gary Guo
2019-03-27 7:06 ` Christoph Hellwig
2019-03-28 6:45 ` Anup Patel
2019-03-27 0:41 ` [PATCH v4 3/5] riscv: fix sbi_remote_sfence_vma{,_asid} Gary Guo
2019-03-27 7:08 ` Christoph Hellwig
2019-03-28 6:47 ` Anup Patel
2019-03-27 0:41 ` [PATCH v4 4/5] riscv: rewrite tlb flush for performance Gary Guo
2019-03-27 7:25 ` Christoph Hellwig
2019-03-27 13:56 ` Gary Guo
2019-03-28 16:17 ` Christoph Hellwig
2019-03-28 16:39 ` Gary Guo
2019-03-28 16:55 ` Christoph Hellwig
2019-03-27 0:41 ` [PATCH v4 2/5] riscv: move switch_mm to its own file Gary Guo
2019-03-27 7:08 ` Christoph Hellwig
2019-03-27 7:18 ` Christoph Hellwig
2019-03-28 6:47 ` Anup Patel
2019-03-27 0:41 ` Gary Guo [this message]
2019-03-27 7:31 ` [PATCH v4 5/5] riscv: implement IPI-based remote TLB shootdown Christoph Hellwig
2019-03-27 14:03 ` Gary Guo
2019-03-28 16:36 ` Christoph Hellwig
2019-03-28 16:47 ` Gary Guo
2019-03-28 16:57 ` Christoph Hellwig
2019-03-28 6:50 ` Anup Patel
2019-04-10 7:04 ` [PATCH v4 0/5] TLB/I$ flush cleanups and improvements Christoph Hellwig
2019-04-10 9:01 ` Anup Patel
2019-04-10 10:11 ` Christoph Hellwig
2019-04-10 10:22 ` Anup Patel
2019-04-11 1:24 ` Atish Patra
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