From: Zong Li <zong.li@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, sboyd@kernel.org,
schwab@linux-m68k.org, pragnesh.patel@openfive.com,
aou@eecs.berkeley.edu, mturquette@baylibre.com,
yash.shah@sifive.com, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Pragnesh Patel <pragnesh.patel@sifive.com>, Zong Li <zong.li@sifive.com>
Subject: [PATCH v7 4/5] clk: sifive: Fix the wrong bit field shift
Date: Wed, 9 Dec 2020 17:49:15 +0800 [thread overview]
Message-ID: <20201209094916.17383-5-zong.li@sifive.com> (raw)
In-Reply-To: <20201209094916.17383-1-zong.li@sifive.com>
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 7e509dfb72d1..88493f3b9edf 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -59,7 +59,7 @@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@ -81,7 +81,7 @@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
--
2.29.2
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next prev parent reply other threads:[~2020-12-09 9:49 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-09 9:49 [PATCH v7 0/5] clk: add driver for the SiFive FU740 Zong Li
2020-12-09 9:49 ` [PATCH v7 1/5] clk: sifive: Extract prci core to common base Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 2/5] clk: sifive: Use common name for prci configuration Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` Zong Li [this message]
2020-12-16 20:21 ` [PATCH v7 4/5] clk: sifive: Fix the wrong bit field shift Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 5/5] clk: sifive: Add clock enable and disable ops Zong Li
2020-12-16 20:21 ` Stephen Boyd
2021-03-16 19:45 ` [PATCH v7 0/5] clk: add driver for the SiFive FU740 Andreas Schwab
2021-03-18 2:07 ` Zong Li
2021-03-19 8:20 ` Zong Li
2021-03-19 8:44 ` Yixun Lan
2021-03-19 8:49 ` Andreas Schwab
2021-03-24 10:36 ` Andreas Schwab
2021-03-25 3:21 ` Zong Li
2021-03-25 9:22 ` Andreas Schwab
2021-03-26 9:10 ` Zong Li
2021-03-26 9:23 ` Andreas Schwab
2021-03-29 10:18 ` Zong Li
2021-03-29 10:37 ` Andreas Schwab
2021-03-31 8:11 ` Zong Li
2021-04-12 11:31 ` Andreas Schwab
2021-04-14 14:13 ` Zong Li
2021-05-11 8:53 ` Yixun Lan
2021-05-19 15:53 ` Zong Li
2021-05-19 18:17 ` Geert Uytterhoeven
2021-05-21 10:34 ` Zong Li
2021-05-21 12:52 ` Zong Li
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