From: Zong Li <zong.li@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com, sboyd@kernel.org,
schwab@linux-m68k.org, pragnesh.patel@openfive.com,
aou@eecs.berkeley.edu, mturquette@baylibre.com,
yash.shah@sifive.com, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v7 0/5] clk: add driver for the SiFive FU740
Date: Wed, 9 Dec 2020 17:49:11 +0800 [thread overview]
Message-ID: <20201209094916.17383-1-zong.li@sifive.com> (raw)
Add a driver for the SiFive FU740 PRCI IP block, which handles more
clocks than FU540. These patches also refactor the original
implementation by spliting the dependent-code of fu540 and fu740
respectively.
We also add a separate patch for DT binding documentation of FU740 PRCI:
https://patchwork.kernel.org/project/linux-riscv/patch/20201126030043.67390-1-zong.li@sifive.com/
Changed in v7:
- Pick changes in v5 back up into this patch series.
Changed in v6:
- Modify the patch "Add clock enable and disable ops"
by Pragnesh. The changes as follows:
- Remove spin lock in enable and disable functions
- Call enable_bypass() before PLL output disable
- Rebase code to Linux v5.10-rc7
Changed in v5:
- Fix copyright format
- Add a link of documentation in commit message
- Modify build dependency for sifive-prci.c
- Add enable and disable functions by Pragnesh Patel
Changed in v4:
- Fix the wrong enable bit field shift for FU540 and FU740.
Changed in v3:
- Fix the wrong enable bit field shift for FU740.
Changed in v2:
- Remove the macro definition for __prci_clock_array.
- Indicate the functional changes in commit message.
- Using option -M and -C to create patches.
- Rebase code to kernel v5.10-rc3.
Pragnesh Patel (1):
clk: sifive: Add clock enable and disable ops
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Fix the wrong bit field shift
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 8 +-
drivers/clk/sifive/Makefile | 2 +-
drivers/clk/sifive/fu540-prci.c | 598 +-----------------
drivers/clk/sifive/fu540-prci.h | 21 +
drivers/clk/sifive/fu740-prci.c | 120 ++++
drivers/clk/sifive/fu740-prci.h | 21 +
drivers/clk/sifive/sifive-prci.c | 574 +++++++++++++++++
drivers/clk/sifive/sifive-prci.h | 299 +++++++++
include/dt-bindings/clock/sifive-fu740-prci.h | 23 +
10 files changed, 1091 insertions(+), 577 deletions(-)
create mode 100644 drivers/clk/sifive/fu540-prci.h
create mode 100644 drivers/clk/sifive/fu740-prci.c
create mode 100644 drivers/clk/sifive/fu740-prci.h
create mode 100644 drivers/clk/sifive/sifive-prci.c
create mode 100644 drivers/clk/sifive/sifive-prci.h
create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
--
2.29.2
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next reply other threads:[~2020-12-09 9:49 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-09 9:49 Zong Li [this message]
2020-12-09 9:49 ` [PATCH v7 1/5] clk: sifive: Extract prci core to common base Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 2/5] clk: sifive: Use common name for prci configuration Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 3/5] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 4/5] clk: sifive: Fix the wrong bit field shift Zong Li
2020-12-16 20:21 ` Stephen Boyd
2020-12-09 9:49 ` [PATCH v7 5/5] clk: sifive: Add clock enable and disable ops Zong Li
2020-12-16 20:21 ` Stephen Boyd
2021-03-16 19:45 ` [PATCH v7 0/5] clk: add driver for the SiFive FU740 Andreas Schwab
2021-03-18 2:07 ` Zong Li
2021-03-19 8:20 ` Zong Li
2021-03-19 8:44 ` Yixun Lan
2021-03-19 8:49 ` Andreas Schwab
2021-03-24 10:36 ` Andreas Schwab
2021-03-25 3:21 ` Zong Li
2021-03-25 9:22 ` Andreas Schwab
2021-03-26 9:10 ` Zong Li
2021-03-26 9:23 ` Andreas Schwab
2021-03-29 10:18 ` Zong Li
2021-03-29 10:37 ` Andreas Schwab
2021-03-31 8:11 ` Zong Li
2021-04-12 11:31 ` Andreas Schwab
2021-04-14 14:13 ` Zong Li
2021-05-11 8:53 ` Yixun Lan
2021-05-19 15:53 ` Zong Li
2021-05-19 18:17 ` Geert Uytterhoeven
2021-05-21 10:34 ` Zong Li
2021-05-21 12:52 ` Zong Li
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