From: Prabhakar <prabhakar.csengg@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@rivosinc.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Date: Fri, 28 Oct 2022 17:59:18 +0100 [thread overview]
Message-ID: <20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com> (raw)
In-Reply-To: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we
will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's.
r9a07g043f.dtsi includes RZ/Five SoC specific blocks.
Below are the RZ/Five SoC specific blocks added in the initial DTSI which
can be used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- PLIC
[0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v4 -> v5
* Fixed riscv,ndev value (should be 511)
* Reworked completely (sort of new patch)
v3 -> v4
* No change
v2 -> v3
* Fixed clock entry for CPU core
* Fixed timebase frequency to 12MHz
* Fixed sorting of the nodes
* Included RB tags
v1 -> v2
* Dropped including makefile change
* Updated ndev count
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++
1 file changed, 57 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
new file mode 100644
index 000000000000..50134be548f5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
+
+#include <arm64/renesas/r9a07g043.dtsi>
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <12000000>;
+
+ cpu0: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+};
+
+&soc {
+ interrupt-parent = <&plic>;
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <511>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+};
--
2.25.1
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next prev parent reply other threads:[~2022-10-28 17:31 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar
2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-10-29 4:20 ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-10-29 4:20 ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
2022-10-29 4:18 ` Guo Ren
2022-11-08 15:37 ` Geert Uytterhoeven
2022-10-28 16:59 ` Prabhakar [this message]
2022-10-29 4:25 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Guo Ren
2022-10-29 19:10 ` Lad, Prabhakar
2022-10-30 0:02 ` Guo Ren
2022-10-30 18:16 ` Conor Dooley
2022-10-30 22:27 ` Lad, Prabhakar
2022-10-30 22:39 ` Conor Dooley
2022-10-31 1:11 ` Guo Ren
2022-10-31 0:45 ` Guo Ren
2022-10-30 22:23 ` Lad, Prabhakar
2022-11-08 15:43 ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-10-29 4:26 ` Guo Ren
2022-10-29 19:14 ` Lad, Prabhakar
2022-11-08 15:44 ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar
2022-10-29 4:27 ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-10-29 4:28 ` Guo Ren
2022-11-08 15:51 ` Geert Uytterhoeven
2022-11-08 16:06 ` Lad, Prabhakar
2022-11-08 16:12 ` Geert Uytterhoeven
2022-11-08 17:22 ` Lad, Prabhakar
2022-11-08 19:19 ` Geert Uytterhoeven
2022-11-08 22:01 ` Lad, Prabhakar
2022-11-09 7:46 ` Geert Uytterhoeven
2022-11-09 9:16 ` Lad, Prabhakar
2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley
2022-10-30 22:37 ` Lad, Prabhakar
2022-10-30 22:45 ` Conor Dooley
2022-10-30 23:01 ` Lad, Prabhakar
2022-11-07 18:03 ` Lad, Prabhakar
2022-11-07 18:17 ` Conor Dooley
2022-11-08 16:02 ` Geert Uytterhoeven
2022-11-08 19:29 ` Conor Dooley
2022-11-09 19:55 ` Palmer Dabbelt
2022-11-09 21:21 ` Conor Dooley
2022-11-10 16:17 ` Geert Uytterhoeven
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