Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC

From: Conor Dooley <conor@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@rivosinc.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
Date: Tue, 8 Nov 2022 19:29:04 +0000	[thread overview]
Message-ID: <Y2quAB1zSGAvOFzD@spud> (raw)
In-Reply-To: <CAMuHMdXjZGTNM7pUqxwXd08bjuPEFUuUwKFGx01FVCqOGnc6hQ@mail.gmail.com>

On Tue, Nov 08, 2022 at 05:02:57PM +0100, Geert Uytterhoeven wrote:
> Hi Conor,
> On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> > Geert, are you waiting for an ack from Palmer?
> 
> I can take:
>   - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
> Renesas RZ/Five SoC
>   - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
> RZ/Five SMARC EVK
>   - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
> (4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
> them to the SoC-people.
> 
> I can take
>   - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
>   - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
> with an ack from Palmer.
> 
> The rest
>   - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
>   - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
> should probably go through the riscv tree, to avoid merge conflicts
> when support for other SoCs is added?

Or depending on the outcome of [0], maybe I take the dt-binding stuff?

Either way, looks like an ack from Palmer is needed for 3 & 7. I can do
the video call version of a ping on that tomorrow at the pw sync thing.

[0] - https://lore.kernel.org/linux-riscv/Y2puchRvbo6+YJSy@wendy/T/#me49f1e779dee210d3ab6fc4bc308dbaed036e1a8

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