From: Guo Ren <guoren@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@rivosinc.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
Date: Sat, 29 Oct 2022 12:20:57 +0800 [thread overview]
Message-ID: <CAJF2gTSaEi=Hjy+57bxNFSKBj4-_ayeh+=9qtX9HXsK3pw3LUw@mail.gmail.com> (raw)
In-Reply-To: <20221028165921.94487-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
> More details about Andes AX45MP core can be found here:
> [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4 -> v5
> * Included RB tag from Conor
>
> v3 -> v4
> * No change
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * Included ack from Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index ae7963e99225..2bf91829c8de 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -28,6 +28,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - andestech,ax45mp
Reviewed-by: Guo Ren <guoren@kernel.org>
> - canaan,k210
> - sifive,bullet0
> - sifive,e5
> --
> 2.25.1
>
--
Best Regards
Guo Ren
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next prev parent reply other threads:[~2022-10-29 4:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar
2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-10-29 4:20 ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-10-29 4:20 ` Guo Ren [this message]
2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar
2022-10-29 4:18 ` Guo Ren
2022-11-08 15:37 ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-10-29 4:25 ` Guo Ren
2022-10-29 19:10 ` Lad, Prabhakar
2022-10-30 0:02 ` Guo Ren
2022-10-30 18:16 ` Conor Dooley
2022-10-30 22:27 ` Lad, Prabhakar
2022-10-30 22:39 ` Conor Dooley
2022-10-31 1:11 ` Guo Ren
2022-10-31 0:45 ` Guo Ren
2022-10-30 22:23 ` Lad, Prabhakar
2022-11-08 15:43 ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-10-29 4:26 ` Guo Ren
2022-10-29 19:14 ` Lad, Prabhakar
2022-11-08 15:44 ` Geert Uytterhoeven
2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar
2022-10-29 4:27 ` Guo Ren
2022-10-28 16:59 ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
2022-10-29 4:28 ` Guo Ren
2022-11-08 15:51 ` Geert Uytterhoeven
2022-11-08 16:06 ` Lad, Prabhakar
2022-11-08 16:12 ` Geert Uytterhoeven
2022-11-08 17:22 ` Lad, Prabhakar
2022-11-08 19:19 ` Geert Uytterhoeven
2022-11-08 22:01 ` Lad, Prabhakar
2022-11-09 7:46 ` Geert Uytterhoeven
2022-11-09 9:16 ` Lad, Prabhakar
2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley
2022-10-30 22:37 ` Lad, Prabhakar
2022-10-30 22:45 ` Conor Dooley
2022-10-30 23:01 ` Lad, Prabhakar
2022-11-07 18:03 ` Lad, Prabhakar
2022-11-07 18:17 ` Conor Dooley
2022-11-08 16:02 ` Geert Uytterhoeven
2022-11-08 19:29 ` Conor Dooley
2022-11-09 19:55 ` Palmer Dabbelt
2022-11-09 21:21 ` Conor Dooley
2022-11-10 16:17 ` Geert Uytterhoeven
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