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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
To: Lee Jones <lee@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Emil Renner Berthing <kernel@esmil.dk>,
	Conor Dooley <conor@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Jose Abreu <joabreu@synopsys.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Yanhong Wang <yanhong.wang@starfivetech.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org, kernel@collabora.com
Subject: [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node
Date: Sat, 11 Feb 2023 05:18:19 +0200	[thread overview]
Message-ID: <20230211031821.976408-11-cristian.ciocaltea@collabora.com> (raw)
In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com>

Provide a DT node for the Sifive Composable Cache controller found on
the StarFive JH7100 SoC.

Note this is also used to support non-coherent DMA.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 7109e70fdab8..88f91bc5753b 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -32,6 +32,7 @@ U74_0: cpu@0 {
 			i-tlb-sets = <1>;
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 
@@ -57,6 +58,7 @@ U74_1: cpu@1 {
 			i-tlb-sets = <1>;
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 
@@ -116,6 +118,20 @@ soc {
 		ranges;
 		dma-noncoherent;
 
+		ccache: cache-controller@2010000 {
+			compatible = "starfive,jh7100-ccache", "cache";
+			reg = <0x0 0x2010000 0x0 0x1000>,
+			      <0x0 0x8000000 0x0 0x2000000>;
+			reg-names = "control", "sideband";
+			interrupts = <128>, <130>, <131>, <129>;
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			uncached-offset = <0xf 0x80000000>;
+		};
+
 		clint: clint@2000000 {
 			compatible = "starfive,jh7100-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
-- 
2.39.1


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  parent reply	other threads:[~2023-02-11  3:35 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-11  3:18 [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible " Cristian Ciocaltea
2023-02-13  9:20   ` Krzysztof Kozlowski
2023-02-14 20:40   ` Conor Dooley
2023-02-15 13:11     ` Emil Renner Berthing
2023-03-20 23:46     ` Palmer Dabbelt
2023-02-11  3:18 ` [PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property Cristian Ciocaltea
2023-02-13  9:23   ` Krzysztof Kozlowski
2023-02-14 17:58     ` Cristian Ciocaltea
2023-02-16 21:53   ` Conor Dooley
2023-02-11  3:18 ` [PATCH 03/12] soc: sifive: ccache: Add StarFive JH7100 support Cristian Ciocaltea
2023-03-06 23:32   ` Conor Dooley
2023-03-06 23:46     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling Cristian Ciocaltea
2023-02-16 18:50   ` Conor Dooley
2023-02-19 21:32     ` Emil Renner Berthing
2023-02-20 11:43       ` Conor Dooley
2023-02-11  3:18 ` [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Cristian Ciocaltea
2023-02-13  8:30   ` Ben Dooks
2023-02-14 18:06     ` Cristian Ciocaltea
2023-02-14 18:17       ` Conor Dooley
2023-02-11  3:18 ` [PATCH 06/12] dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible Cristian Ciocaltea
2023-02-13  9:23   ` Krzysztof Kozlowski
2023-03-03 11:52   ` Lee Jones
2023-02-11  3:18 ` [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11 16:01   ` Andrew Lunn
2023-02-15  0:34     ` Cristian Ciocaltea
2023-02-15 13:01       ` Andrew Lunn
2023-02-16 15:51         ` Cristian Ciocaltea
2023-02-16 17:54           ` Andrew Lunn
2023-02-17  0:32             ` Cristian Ciocaltea
2023-02-17 13:30               ` Andrew Lunn
2023-02-17 15:25                 ` Cristian Ciocaltea
2023-02-13  9:25   ` Krzysztof Kozlowski
2023-02-11  3:18 ` [PATCH 08/12] net: stmmac: Add glue layer for " Cristian Ciocaltea
2023-02-11 16:11   ` Andrew Lunn
2023-02-15  0:08     ` Cristian Ciocaltea
2023-02-15 11:20       ` Emil Renner Berthing
2023-02-15 11:51         ` Cristian Ciocaltea
2023-02-15 12:51       ` Andrew Lunn
2023-02-13  9:26   ` Krzysztof Kozlowski
2023-02-14 18:12     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 09/12] riscv: dts: starfive: Add dma-noncoherent for " Cristian Ciocaltea
2023-02-11  3:18 ` Cristian Ciocaltea [this message]
2023-02-11  3:18 ` [PATCH 11/12] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Cristian Ciocaltea
2023-02-13  9:26   ` Krzysztof Kozlowski
2023-02-14 18:15     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 12/12] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Cristian Ciocaltea
2023-02-11 11:11 ` [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Conor Dooley
2023-02-11 11:53   ` Cristian Ciocaltea

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