From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
To: Lee Jones <lee@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Richard Cochran <richardcochran@gmail.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
Yanhong Wang <yanhong.wang@starfivetech.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, kernel@collabora.com
Subject: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC
Date: Sat, 11 Feb 2023 05:18:10 +0200 [thread overview]
Message-ID: <20230211031821.976408-2-cristian.ciocaltea@collabora.com> (raw)
In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com>
Document the compatible for the SiFive Composable Cache Controller found
on the StarFive JH7100 SoC.
This also requires extending the 'reg' property to handle distinct
ranges, as specified via 'reg-names'.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
.../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index 31d20efaa6d3..2b864b2f12c9 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -25,6 +25,7 @@ select:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
required:
- compatible
@@ -37,6 +38,7 @@ properties:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- const: cache
- items:
- const: starfive,jh7110-ccache
@@ -70,7 +72,13 @@ properties:
- description: DirFail interrupt
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: control
+ - const: sideband
next-level-cache: true
@@ -89,6 +97,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -106,12 +115,29 @@ allOf:
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7100-ccache
+
+ then:
+ properties:
+ reg:
+ maxItems: 2
+
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
- if:
properties:
compatible:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.39.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-11 3:25 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-11 3:18 [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11 3:18 ` Cristian Ciocaltea [this message]
2023-02-13 9:20 ` [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible " Krzysztof Kozlowski
2023-02-14 20:40 ` Conor Dooley
2023-02-15 13:11 ` Emil Renner Berthing
2023-03-20 23:46 ` Palmer Dabbelt
2023-02-11 3:18 ` [PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property Cristian Ciocaltea
2023-02-13 9:23 ` Krzysztof Kozlowski
2023-02-14 17:58 ` Cristian Ciocaltea
2023-02-16 21:53 ` Conor Dooley
2023-02-11 3:18 ` [PATCH 03/12] soc: sifive: ccache: Add StarFive JH7100 support Cristian Ciocaltea
2023-03-06 23:32 ` Conor Dooley
2023-03-06 23:46 ` Cristian Ciocaltea
2023-02-11 3:18 ` [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling Cristian Ciocaltea
2023-02-16 18:50 ` Conor Dooley
2023-02-19 21:32 ` Emil Renner Berthing
2023-02-20 11:43 ` Conor Dooley
2023-02-11 3:18 ` [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Cristian Ciocaltea
2023-02-13 8:30 ` Ben Dooks
2023-02-14 18:06 ` Cristian Ciocaltea
2023-02-14 18:17 ` Conor Dooley
2023-02-11 3:18 ` [PATCH 06/12] dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible Cristian Ciocaltea
2023-02-13 9:23 ` Krzysztof Kozlowski
2023-03-03 11:52 ` Lee Jones
2023-02-11 3:18 ` [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11 16:01 ` Andrew Lunn
2023-02-15 0:34 ` Cristian Ciocaltea
2023-02-15 13:01 ` Andrew Lunn
2023-02-16 15:51 ` Cristian Ciocaltea
2023-02-16 17:54 ` Andrew Lunn
2023-02-17 0:32 ` Cristian Ciocaltea
2023-02-17 13:30 ` Andrew Lunn
2023-02-17 15:25 ` Cristian Ciocaltea
2023-02-13 9:25 ` Krzysztof Kozlowski
2023-02-11 3:18 ` [PATCH 08/12] net: stmmac: Add glue layer for " Cristian Ciocaltea
2023-02-11 16:11 ` Andrew Lunn
2023-02-15 0:08 ` Cristian Ciocaltea
2023-02-15 11:20 ` Emil Renner Berthing
2023-02-15 11:51 ` Cristian Ciocaltea
2023-02-15 12:51 ` Andrew Lunn
2023-02-13 9:26 ` Krzysztof Kozlowski
2023-02-14 18:12 ` Cristian Ciocaltea
2023-02-11 3:18 ` [PATCH 09/12] riscv: dts: starfive: Add dma-noncoherent for " Cristian Ciocaltea
2023-02-11 3:18 ` [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node Cristian Ciocaltea
2023-02-11 3:18 ` [PATCH 11/12] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Cristian Ciocaltea
2023-02-13 9:26 ` Krzysztof Kozlowski
2023-02-14 18:15 ` Cristian Ciocaltea
2023-02-11 3:18 ` [PATCH 12/12] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Cristian Ciocaltea
2023-02-11 11:11 ` [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Conor Dooley
2023-02-11 11:53 ` Cristian Ciocaltea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230211031821.976408-2-cristian.ciocaltea@collabora.com \
--to=cristian.ciocaltea@collabora.com \
--cc=alexandre.torgue@foss.st.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=joabreu@synopsys.com \
--cc=kernel@collabora.com \
--cc=kernel@esmil.dk \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kuba@kernel.org \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=peppe.cavallaro@st.com \
--cc=richardcochran@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sagar.kadam@sifive.com \
--cc=yanhong.wang@starfivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).