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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: Conor Dooley <conor@kernel.org>
Cc: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
	Lee Jones <lee@kernel.org>,  Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	"David S. Miller" <davem@davemloft.net>,
	 Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	 Emil Renner Berthing <kernel@esmil.dk>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	 Jose Abreu <joabreu@synopsys.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	 Richard Cochran <richardcochran@gmail.com>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	 Yanhong Wang <yanhong.wang@starfivetech.com>,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	netdev@vger.kernel.org,  linux-riscv@lists.infradead.org,
	linux-stm32@st-md-mailman.stormreply.com,
	 linux-arm-kernel@lists.infradead.org, kernel@collabora.com,
	 daire.mcnamara@microchip.com
Subject: Re: [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling
Date: Sun, 19 Feb 2023 22:32:52 +0100	[thread overview]
Message-ID: <CAJM55Z_poY3dVu9fQ1W1VQw3V=8VdVKc1+qUcdHduM1aAveJUQ@mail.gmail.com> (raw)
In-Reply-To: <Y+567t+kDjZI+fbo@spud>

On Thu, 16 Feb 2023 at 19:51, Conor Dooley <conor@kernel.org> wrote:
>
> Emil,
>
> +CC Daire
>
> On Sat, Feb 11, 2023 at 05:18:13AM +0200, Cristian Ciocaltea wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add functions to flush the caches and handle non-coherent DMA.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > [replace <asm/cacheflush.h> with <linux/cacheflush.h>]
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> > ---
>
> > +void *sifive_ccache_set_uncached(void *addr, size_t size)
> > +{
> > +     phys_addr_t phys_addr = __pa(addr) + uncached_offset;
> > +     void *mem_base;
> > +
> > +     mem_base = memremap(phys_addr, size, MEMREMAP_WT);
> > +     if (!mem_base) {
> > +             pr_err("%s memremap failed for addr %p\n", __func__, addr);
> > +             return ERR_PTR(-EINVAL);
> > +     }
> > +
> > +     return mem_base;
> > +}
>
> The rest of this I either get b/c we did it, or will become moot so I
> amn't worried about it, but can you please explain this, in particular
> the memremap that you're doing here?

No, I can't really. As we talked about it's also based on a prototype
by Atish. I'm sure you know that the general idea is that we want to
return a pointer that accesses the same physical memory, but through
the uncached alias. I can't tell you exactly why it's done this way
though, sorry.

/Emil

> Cheers,
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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  reply	other threads:[~2023-02-19 21:33 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-11  3:18 [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible " Cristian Ciocaltea
2023-02-13  9:20   ` Krzysztof Kozlowski
2023-02-14 20:40   ` Conor Dooley
2023-02-15 13:11     ` Emil Renner Berthing
2023-03-20 23:46     ` Palmer Dabbelt
2023-02-11  3:18 ` [PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property Cristian Ciocaltea
2023-02-13  9:23   ` Krzysztof Kozlowski
2023-02-14 17:58     ` Cristian Ciocaltea
2023-02-16 21:53   ` Conor Dooley
2023-02-11  3:18 ` [PATCH 03/12] soc: sifive: ccache: Add StarFive JH7100 support Cristian Ciocaltea
2023-03-06 23:32   ` Conor Dooley
2023-03-06 23:46     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling Cristian Ciocaltea
2023-02-16 18:50   ` Conor Dooley
2023-02-19 21:32     ` Emil Renner Berthing [this message]
2023-02-20 11:43       ` Conor Dooley
2023-02-11  3:18 ` [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Cristian Ciocaltea
2023-02-13  8:30   ` Ben Dooks
2023-02-14 18:06     ` Cristian Ciocaltea
2023-02-14 18:17       ` Conor Dooley
2023-02-11  3:18 ` [PATCH 06/12] dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible Cristian Ciocaltea
2023-02-13  9:23   ` Krzysztof Kozlowski
2023-03-03 11:52   ` Lee Jones
2023-02-11  3:18 ` [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC Cristian Ciocaltea
2023-02-11 16:01   ` Andrew Lunn
2023-02-15  0:34     ` Cristian Ciocaltea
2023-02-15 13:01       ` Andrew Lunn
2023-02-16 15:51         ` Cristian Ciocaltea
2023-02-16 17:54           ` Andrew Lunn
2023-02-17  0:32             ` Cristian Ciocaltea
2023-02-17 13:30               ` Andrew Lunn
2023-02-17 15:25                 ` Cristian Ciocaltea
2023-02-13  9:25   ` Krzysztof Kozlowski
2023-02-11  3:18 ` [PATCH 08/12] net: stmmac: Add glue layer for " Cristian Ciocaltea
2023-02-11 16:11   ` Andrew Lunn
2023-02-15  0:08     ` Cristian Ciocaltea
2023-02-15 11:20       ` Emil Renner Berthing
2023-02-15 11:51         ` Cristian Ciocaltea
2023-02-15 12:51       ` Andrew Lunn
2023-02-13  9:26   ` Krzysztof Kozlowski
2023-02-14 18:12     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 09/12] riscv: dts: starfive: Add dma-noncoherent for " Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 11/12] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Cristian Ciocaltea
2023-02-13  9:26   ` Krzysztof Kozlowski
2023-02-14 18:15     ` Cristian Ciocaltea
2023-02-11  3:18 ` [PATCH 12/12] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Cristian Ciocaltea
2023-02-11 11:11 ` [PATCH 00/12] Enable networking support for StarFive JH7100 SoC Conor Dooley
2023-02-11 11:53   ` Cristian Ciocaltea

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