* [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
2023-05-29 10:42 ` Conor Dooley
2023-05-26 16:59 ` [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
The CBOM size and whether the HW is noncoherent is known and
determined during booting and won't change after that.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/errata/thead/errata.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index c259dc925ec1..be84b14f0118 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return false;
- riscv_cbom_block_size = L1_CACHE_BYTES;
- riscv_noncoherent_supported();
+ if (stage == RISCV_ALTERNATIVES_BOOT) {
+ riscv_cbom_block_size = L1_CACHE_BYTES;
+ riscv_noncoherent_supported();
+ }
+
return true;
}
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot
2023-05-26 16:59 ` [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
@ 2023-05-29 10:42 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2023-05-29 10:42 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 340 bytes --]
On Sat, May 27, 2023 at 12:59:53AM +0800, Jisheng Zhang wrote:
> The CBOM size and whether the HW is noncoherent is known and
> determined during booting and won't change after that.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Makes sense to me,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
2023-05-26 16:59 ` [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
2023-05-29 10:44 ` Conor Dooley
2023-05-26 16:59 ` [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
` (3 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
The two functions cbo_get_block_size() and riscv_init_cbo_blocksizes()
are only called during booting, mark them as __init.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/mm/cacheflush.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index fca532ddf3ec..fbc59b3f69f2 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -104,9 +104,9 @@ EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
unsigned int riscv_cboz_block_size;
EXPORT_SYMBOL_GPL(riscv_cboz_block_size);
-static void cbo_get_block_size(struct device_node *node,
- const char *name, u32 *block_size,
- unsigned long *first_hartid)
+static void __init cbo_get_block_size(struct device_node *node,
+ const char *name, u32 *block_size,
+ unsigned long *first_hartid)
{
unsigned long hartid;
u32 val;
@@ -126,7 +126,7 @@ static void cbo_get_block_size(struct device_node *node,
}
}
-void riscv_init_cbo_blocksizes(void)
+void __init riscv_init_cbo_blocksizes(void)
{
unsigned long cbom_hartid, cboz_hartid;
u32 cbom_block_size = 0, cboz_block_size = 0;
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init
2023-05-26 16:59 ` [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
@ 2023-05-29 10:44 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2023-05-29 10:44 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 328 bytes --]
On Sat, May 27, 2023 at 12:59:54AM +0800, Jisheng Zhang wrote:
> The two functions cbo_get_block_size() and riscv_init_cbo_blocksizes()
> are only called during booting, mark them as __init.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
2023-05-26 16:59 ` [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
2023-05-26 16:59 ` [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
2023-05-29 10:53 ` Conor Dooley
2023-05-26 16:59 ` [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Jisheng Zhang
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
The noncoherent_supported indicates whether the HW is coherent or not,
it won't change after booting, mark it as __ro_after_init.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d919efab6eba..d51a75864e53 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -10,7 +10,7 @@
#include <linux/mm.h>
#include <asm/cacheflush.h>
-static bool noncoherent_supported;
+static bool noncoherent_supported __ro_after_init;
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init
2023-05-26 16:59 ` [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
@ 2023-05-29 10:53 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2023-05-29 10:53 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 334 bytes --]
On Sat, May 27, 2023 at 12:59:55AM +0800, Jisheng Zhang wrote:
> The noncoherent_supported indicates whether the HW is coherent or not,
> it won't change after booting, mark it as __ro_after_init.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
` (2 preceding siblings ...)
2023-05-26 16:59 ` [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
2023-05-29 11:13 ` Conor Dooley
2023-05-26 16:59 ` [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
2023-05-26 16:59 ` [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Jisheng Zhang
5 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
We will soon take different actions by checking the HW is noncoherent
or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
arch/riscv/include/asm/cacheflush.h | 4 ++--
arch/riscv/kernel/setup.c | 6 +++++-
arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
4 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index be84b14f0118..c192b80a5166 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
static bool errata_probe_cmo(unsigned int stage,
unsigned long arch_id, unsigned long impid)
{
- if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
- return false;
-
- if (arch_id != 0 || impid != 0)
- return false;
+ bool cmo;
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return false;
+ if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
+ (arch_id == 0 && impid == 0))
+ cmo = true;
+ else
+ cmo = false;
+
if (stage == RISCV_ALTERNATIVES_BOOT) {
- riscv_cbom_block_size = L1_CACHE_BYTES;
- riscv_noncoherent_supported();
+ if (cmo)
+ riscv_cbom_block_size = L1_CACHE_BYTES;
+ riscv_noncoherent_supported(cmo);
}
- return true;
+ return cmo;
}
static bool errata_probe_pmu(unsigned int stage,
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index 8091b8bf4883..9d056c9b625a 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
void riscv_init_cbo_blocksizes(void);
#ifdef CONFIG_RISCV_DMA_NONCOHERENT
-void riscv_noncoherent_supported(void);
+void riscv_noncoherent_supported(bool cmo);
#else
-static inline void riscv_noncoherent_supported(void) {}
+static inline void riscv_noncoherent_supported(bool cmo) {}
#endif
/*
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 36b026057503..565f3e20169b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -264,6 +264,7 @@ static void __init parse_dtb(void)
void __init setup_arch(char **cmdline_p)
{
+ bool cmo;
parse_dtb();
setup_initial_init_mm(_stext, _etext, _edata, _end);
@@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
apply_boot_alternatives();
if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
riscv_isa_extension_available(NULL, ZICBOM))
- riscv_noncoherent_supported();
+ cmo = true;
+ else
+ cmo = false;
+ riscv_noncoherent_supported(cmo);
}
static int __init topology_init(void)
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d51a75864e53..0e172e2b4751 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
dev->dma_coherent = coherent;
}
-void riscv_noncoherent_supported(void)
+void riscv_noncoherent_supported(bool cmo)
{
- WARN(!riscv_cbom_block_size,
- "Non-coherent DMA support enabled without a block size\n");
- noncoherent_supported = true;
+ if (cmo) {
+ WARN(!riscv_cbom_block_size,
+ "Non-coherent DMA support enabled without a block size\n");
+ noncoherent_supported = true;
+ }
}
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-26 16:59 ` [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Jisheng Zhang
@ 2023-05-29 11:13 ` Conor Dooley
2023-05-31 15:24 ` Jisheng Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2023-05-29 11:13 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 4507 bytes --]
Hey Jisheng,
On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> We will soon take different actions by checking the HW is noncoherent
> or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
> arch/riscv/include/asm/cacheflush.h | 4 ++--
> arch/riscv/kernel/setup.c | 6 +++++-
> arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
> 4 files changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index be84b14f0118..c192b80a5166 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> static bool errata_probe_cmo(unsigned int stage,
> unsigned long arch_id, unsigned long impid)
> {
> - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> - return false;
> -
> - if (arch_id != 0 || impid != 0)
> - return false;
> + bool cmo;
>
> if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> return false;
>
> + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> + (arch_id == 0 && impid == 0))
> + cmo = true;
> + else
> + cmo = false;
> +
> if (stage == RISCV_ALTERNATIVES_BOOT) {
> - riscv_cbom_block_size = L1_CACHE_BYTES;
> - riscv_noncoherent_supported();
> + if (cmo)
> + riscv_cbom_block_size = L1_CACHE_BYTES;
> + riscv_noncoherent_supported(cmo);
> }
>
> - return true;
> + return cmo;
I don't really understand the changes that you are making to this
function, so that is tries really hard to call
riscv_noncoherent_supported(). Why do we need to always call the function
in the erratum's probe function, if the erratum is not detected, given
that riscv_noncoherent_supported() is called immediately after
apply_boot_alternatives() in setup_arch()?
> }
>
> static bool errata_probe_pmu(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index 8091b8bf4883..9d056c9b625a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
> void riscv_init_cbo_blocksizes(void);
>
> #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> -void riscv_noncoherent_supported(void);
> +void riscv_noncoherent_supported(bool cmo);
I think it would "read better" if you renamed this variable to
"have_cmo".
> #else
> -static inline void riscv_noncoherent_supported(void) {}
> +static inline void riscv_noncoherent_supported(bool cmo) {}
> #endif
>
> /*
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 36b026057503..565f3e20169b 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -264,6 +264,7 @@ static void __init parse_dtb(void)
>
> void __init setup_arch(char **cmdline_p)
> {
> + bool cmo;
> parse_dtb();
> setup_initial_init_mm(_stext, _etext, _edata, _end);
>
> @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
> apply_boot_alternatives();
> if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> riscv_isa_extension_available(NULL, ZICBOM))
> - riscv_noncoherent_supported();
> + cmo = true;
> + else
> + cmo = false;
> + riscv_noncoherent_supported(cmo);
As a nit, could you put a newline before the call to
riscv_noncoherent_supported()?
> }
>
> static int __init topology_init(void)
> diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> index d51a75864e53..0e172e2b4751 100644
> --- a/arch/riscv/mm/dma-noncoherent.c
> +++ b/arch/riscv/mm/dma-noncoherent.c
> @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> dev->dma_coherent = coherent;
> }
>
> -void riscv_noncoherent_supported(void)
> +void riscv_noncoherent_supported(bool cmo)
> {
> - WARN(!riscv_cbom_block_size,
> - "Non-coherent DMA support enabled without a block size\n");
> - noncoherent_supported = true;
> + if (cmo) {
> + WARN(!riscv_cbom_block_size,
> + "Non-coherent DMA support enabled without a block size\n");
> + noncoherent_supported = true;
> + }
The other places that we do a WARN() because of screwed up devicetrees
for CMO things, we do a WARN_TAINT(CPU_OUT_OF_SPEC). Should we do the
same here too?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-29 11:13 ` Conor Dooley
@ 2023-05-31 15:24 ` Jisheng Zhang
2023-05-31 15:28 ` Jisheng Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-31 15:24 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> Hey Jisheng,
Hi Conor,
>
> On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > We will soon take different actions by checking the HW is noncoherent
> > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> > arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
> > arch/riscv/include/asm/cacheflush.h | 4 ++--
> > arch/riscv/kernel/setup.c | 6 +++++-
> > arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
> > 4 files changed, 24 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index be84b14f0118..c192b80a5166 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > static bool errata_probe_cmo(unsigned int stage,
> > unsigned long arch_id, unsigned long impid)
> > {
> > - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > - return false;
> > -
> > - if (arch_id != 0 || impid != 0)
> > - return false;
> > + bool cmo;
> >
> > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > return false;
> >
> > + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > + (arch_id == 0 && impid == 0))
> > + cmo = true;
> > + else
> > + cmo = false;
> > +
> > if (stage == RISCV_ALTERNATIVES_BOOT) {
> > - riscv_cbom_block_size = L1_CACHE_BYTES;
> > - riscv_noncoherent_supported();
> > + if (cmo)
> > + riscv_cbom_block_size = L1_CACHE_BYTES;
> > + riscv_noncoherent_supported(cmo);
> > }
> >
> > - return true;
> > + return cmo;
>
> I don't really understand the changes that you are making to this
> function, so that is tries really hard to call
> riscv_noncoherent_supported(). Why do we need to always call the function
> in the erratum's probe function, if the erratum is not detected, given
In one unified kernel Image, to support both coherent and noncoherent
platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.
Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
to 1. The notice action is done in patch 5:
+ } else {
+ dma_cache_alignment = 1;
> that riscv_noncoherent_supported() is called immediately after
> apply_boot_alternatives() in setup_arch()?
>
> > }
> >
> > static bool errata_probe_pmu(unsigned int stage,
> > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> > index 8091b8bf4883..9d056c9b625a 100644
> > --- a/arch/riscv/include/asm/cacheflush.h
> > +++ b/arch/riscv/include/asm/cacheflush.h
> > @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
> > void riscv_init_cbo_blocksizes(void);
> >
> > #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > -void riscv_noncoherent_supported(void);
> > +void riscv_noncoherent_supported(bool cmo);
>
> I think it would "read better" if you renamed this variable to
> "have_cmo".
>
> > #else
> > -static inline void riscv_noncoherent_supported(void) {}
> > +static inline void riscv_noncoherent_supported(bool cmo) {}
> > #endif
> >
> > /*
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 36b026057503..565f3e20169b 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -264,6 +264,7 @@ static void __init parse_dtb(void)
> >
> > void __init setup_arch(char **cmdline_p)
> > {
> > + bool cmo;
> > parse_dtb();
> > setup_initial_init_mm(_stext, _etext, _edata, _end);
> >
> > @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
> > apply_boot_alternatives();
> > if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> > riscv_isa_extension_available(NULL, ZICBOM))
> > - riscv_noncoherent_supported();
> > + cmo = true;
> > + else
> > + cmo = false;
> > + riscv_noncoherent_supported(cmo);
>
> As a nit, could you put a newline before the call to
> riscv_noncoherent_supported()?
>
> > }
> >
> > static int __init topology_init(void)
> > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > index d51a75864e53..0e172e2b4751 100644
> > --- a/arch/riscv/mm/dma-noncoherent.c
> > +++ b/arch/riscv/mm/dma-noncoherent.c
> > @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> > dev->dma_coherent = coherent;
> > }
> >
> > -void riscv_noncoherent_supported(void)
> > +void riscv_noncoherent_supported(bool cmo)
> > {
> > - WARN(!riscv_cbom_block_size,
> > - "Non-coherent DMA support enabled without a block size\n");
> > - noncoherent_supported = true;
> > + if (cmo) {
> > + WARN(!riscv_cbom_block_size,
> > + "Non-coherent DMA support enabled without a block size\n");
> > + noncoherent_supported = true;
> > + }
>
> The other places that we do a WARN() because of screwed up devicetrees
> for CMO things, we do a WARN_TAINT(CPU_OUT_OF_SPEC). Should we do the
> same here too?
>
> Cheers,
> Conor.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-31 15:24 ` Jisheng Zhang
@ 2023-05-31 15:28 ` Jisheng Zhang
2023-05-31 16:28 ` Conor Dooley
0 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-31 15:28 UTC (permalink / raw)
To: Conor Dooley
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
On Wed, May 31, 2023 at 11:24:19PM +0800, Jisheng Zhang wrote:
> On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> > Hey Jisheng,
>
> Hi Conor,
>
> >
> > On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > > We will soon take different actions by checking the HW is noncoherent
> > > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > > arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
> > > arch/riscv/include/asm/cacheflush.h | 4 ++--
> > > arch/riscv/kernel/setup.c | 6 +++++-
> > > arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
> > > 4 files changed, 24 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > index be84b14f0118..c192b80a5166 100644
> > > --- a/arch/riscv/errata/thead/errata.c
> > > +++ b/arch/riscv/errata/thead/errata.c
> > > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > > static bool errata_probe_cmo(unsigned int stage,
> > > unsigned long arch_id, unsigned long impid)
> > > {
> > > - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > > - return false;
> > > -
> > > - if (arch_id != 0 || impid != 0)
> > > - return false;
> > > + bool cmo;
> > >
> > > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > return false;
> > >
> > > + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > > + (arch_id == 0 && impid == 0))
> > > + cmo = true;
> > > + else
> > > + cmo = false;
> > > +
> > > if (stage == RISCV_ALTERNATIVES_BOOT) {
> > > - riscv_cbom_block_size = L1_CACHE_BYTES;
> > > - riscv_noncoherent_supported();
> > > + if (cmo)
> > > + riscv_cbom_block_size = L1_CACHE_BYTES;
> > > + riscv_noncoherent_supported(cmo);
> > > }
> > >
> > > - return true;
> > > + return cmo;
> >
> > I don't really understand the changes that you are making to this
> > function, so that is tries really hard to call
> > riscv_noncoherent_supported(). Why do we need to always call the function
> > in the erratum's probe function, if the erratum is not detected, given
>
> In one unified kernel Image, to support both coherent and noncoherent
> platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
> kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.
seems adding three words can make it better:
kmalloc meet both cases at the beginning, specifically ...
> Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
> ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
> to 1. The notice action is done in patch 5:
>
> + } else {
> + dma_cache_alignment = 1;
>
>
> > that riscv_noncoherent_supported() is called immediately after
> > apply_boot_alternatives() in setup_arch()?
> >
> > > }
> > >
> > > static bool errata_probe_pmu(unsigned int stage,
> > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> > > index 8091b8bf4883..9d056c9b625a 100644
> > > --- a/arch/riscv/include/asm/cacheflush.h
> > > +++ b/arch/riscv/include/asm/cacheflush.h
> > > @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
> > > void riscv_init_cbo_blocksizes(void);
> > >
> > > #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > > -void riscv_noncoherent_supported(void);
> > > +void riscv_noncoherent_supported(bool cmo);
> >
> > I think it would "read better" if you renamed this variable to
> > "have_cmo".
> >
> > > #else
> > > -static inline void riscv_noncoherent_supported(void) {}
> > > +static inline void riscv_noncoherent_supported(bool cmo) {}
> > > #endif
> > >
> > > /*
> > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > > index 36b026057503..565f3e20169b 100644
> > > --- a/arch/riscv/kernel/setup.c
> > > +++ b/arch/riscv/kernel/setup.c
> > > @@ -264,6 +264,7 @@ static void __init parse_dtb(void)
> > >
> > > void __init setup_arch(char **cmdline_p)
> > > {
> > > + bool cmo;
> > > parse_dtb();
> > > setup_initial_init_mm(_stext, _etext, _edata, _end);
> > >
> > > @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
> > > apply_boot_alternatives();
> > > if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> > > riscv_isa_extension_available(NULL, ZICBOM))
> > > - riscv_noncoherent_supported();
> > > + cmo = true;
> > > + else
> > > + cmo = false;
> > > + riscv_noncoherent_supported(cmo);
> >
> > As a nit, could you put a newline before the call to
> > riscv_noncoherent_supported()?
> >
> > > }
> > >
> > > static int __init topology_init(void)
> > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > > index d51a75864e53..0e172e2b4751 100644
> > > --- a/arch/riscv/mm/dma-noncoherent.c
> > > +++ b/arch/riscv/mm/dma-noncoherent.c
> > > @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> > > dev->dma_coherent = coherent;
> > > }
> > >
> > > -void riscv_noncoherent_supported(void)
> > > +void riscv_noncoherent_supported(bool cmo)
> > > {
> > > - WARN(!riscv_cbom_block_size,
> > > - "Non-coherent DMA support enabled without a block size\n");
> > > - noncoherent_supported = true;
> > > + if (cmo) {
> > > + WARN(!riscv_cbom_block_size,
> > > + "Non-coherent DMA support enabled without a block size\n");
> > > + noncoherent_supported = true;
> > > + }
> >
> > The other places that we do a WARN() because of screwed up devicetrees
> > for CMO things, we do a WARN_TAINT(CPU_OUT_OF_SPEC). Should we do the
> > same here too?
> >
> > Cheers,
> > Conor.
>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-31 15:28 ` Jisheng Zhang
@ 2023-05-31 16:28 ` Conor Dooley
2023-06-01 3:40 ` Jisheng Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2023-05-31 16:28 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 4768 bytes --]
On Wed, May 31, 2023 at 11:28:22PM +0800, Jisheng Zhang wrote:
> On Wed, May 31, 2023 at 11:24:19PM +0800, Jisheng Zhang wrote:
> > On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> > > On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > > > We will soon take different actions by checking the HW is noncoherent
> > > > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> > > >
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > ---
> > > > arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
> > > > arch/riscv/include/asm/cacheflush.h | 4 ++--
> > > > arch/riscv/kernel/setup.c | 6 +++++-
> > > > arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
> > > > 4 files changed, 24 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > > index be84b14f0118..c192b80a5166 100644
> > > > --- a/arch/riscv/errata/thead/errata.c
> > > > +++ b/arch/riscv/errata/thead/errata.c
> > > > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > > > static bool errata_probe_cmo(unsigned int stage,
> > > > unsigned long arch_id, unsigned long impid)
> > > > {
> > > > - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > > > - return false;
> > > > -
> > > > - if (arch_id != 0 || impid != 0)
> > > > - return false;
> > > > + bool cmo;
> > > >
> > > > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > > return false;
> > > >
> > > > + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > > > + (arch_id == 0 && impid == 0))
> > > > + cmo = true;
> > > > + else
> > > > + cmo = false;
> > > > +
> > > > if (stage == RISCV_ALTERNATIVES_BOOT) {
> > > > - riscv_cbom_block_size = L1_CACHE_BYTES;
> > > > - riscv_noncoherent_supported();
> > > > + if (cmo)
> > > > + riscv_cbom_block_size = L1_CACHE_BYTES;
> > > > + riscv_noncoherent_supported(cmo);
> > > > }
> > > >
> > > > - return true;
> > > > + return cmo;
> > >
> > > I don't really understand the changes that you are making to this
> > > function, so that is tries really hard to call
> > > riscv_noncoherent_supported(). Why do we need to always call the function
> > > in the erratum's probe function, if the erratum is not detected, given
> >
> > In one unified kernel Image, to support both coherent and noncoherent
> > platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
> > kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.
>
> seems adding three words can make it better:
>
> kmalloc meet both cases at the beginning, specifically ...
>
> > Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
> > ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
> > to 1. The notice action is done in patch 5:
> >
> > + } else {
> > + dma_cache_alignment = 1;
> >
> >
> > > that riscv_noncoherent_supported() is called immediately after
> > > apply_boot_alternatives() in setup_arch()?
This bit here is the key part of my confusion. You try really hard in
the errata stuff to call riscv_noncoherent_supported(), which I do
understand is because of the other branch that you add to the function
later in the series.
What I do not understand is why we are not able to rely on the call to
it in setup_arch() to trigger it when we do not have T-HEAD CMOs or
Zicbom.
You've explained why you want to make sure it always gets called during
boot, but my question is about why it looks like it is being called more
than once.
Actually, now that I think of it, what happens on a T-HEAD system where
there is no T-HEAD CMOs, but there is Zicbom. In theory, this could
exist.
Bear with me here a moment in case I am completely wrong, snippet is
from setup_arch()
apply_boot_alternatives();
On my example system, this will trigger, eventually sending us into
errata_probe_cmo(), where we will call riscv_noncoherent_supported()
with false, setting dma_cache_alignment to 1.
if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
riscv_isa_extension_available(NULL, ZICBOM))
cmo = true;
On this system, this will be true.
else
cmo = false;
riscv_noncoherent_supported(cmo);
now riscv_noncoherent_supported() is called with true, and we have
dma_cache_alignment = 1 still. Is that not problematic? Or the inverse,
where the T-HEAD system has its custom CMOs and there is no Zicbom, it
gets called twice with different args too.
There's clearly something fundamental that I am missing here, this seems
like it should be immediately obvious why this either cannot happen or
is not a problem, but I can't see it.
Sorry,
Conor.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
2023-05-31 16:28 ` Conor Dooley
@ 2023-06-01 3:40 ` Jisheng Zhang
0 siblings, 0 replies; 20+ messages in thread
From: Jisheng Zhang @ 2023-06-01 3:40 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel, Catalin Marinas
On Wed, May 31, 2023 at 05:28:56PM +0100, Conor Dooley wrote:
> On Wed, May 31, 2023 at 11:28:22PM +0800, Jisheng Zhang wrote:
> > On Wed, May 31, 2023 at 11:24:19PM +0800, Jisheng Zhang wrote:
> > > On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> > > > On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > > > > We will soon take different actions by checking the HW is noncoherent
> > > > > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> > > > >
> > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > > > ---
> > > > > arch/riscv/errata/thead/errata.c | 19 +++++++++++--------
> > > > > arch/riscv/include/asm/cacheflush.h | 4 ++--
> > > > > arch/riscv/kernel/setup.c | 6 +++++-
> > > > > arch/riscv/mm/dma-noncoherent.c | 10 ++++++----
> > > > > 4 files changed, 24 insertions(+), 15 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > > > index be84b14f0118..c192b80a5166 100644
> > > > > --- a/arch/riscv/errata/thead/errata.c
> > > > > +++ b/arch/riscv/errata/thead/errata.c
> > > > > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > > > > static bool errata_probe_cmo(unsigned int stage,
> > > > > unsigned long arch_id, unsigned long impid)
> > > > > {
> > > > > - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > > > > - return false;
> > > > > -
> > > > > - if (arch_id != 0 || impid != 0)
> > > > > - return false;
> > > > > + bool cmo;
> > > > >
> > > > > if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > > > return false;
> > > > >
> > > > > + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > > > > + (arch_id == 0 && impid == 0))
> > > > > + cmo = true;
> > > > > + else
> > > > > + cmo = false;
> > > > > +
> > > > > if (stage == RISCV_ALTERNATIVES_BOOT) {
> > > > > - riscv_cbom_block_size = L1_CACHE_BYTES;
> > > > > - riscv_noncoherent_supported();
> > > > > + if (cmo)
> > > > > + riscv_cbom_block_size = L1_CACHE_BYTES;
> > > > > + riscv_noncoherent_supported(cmo);
> > > > > }
> > > > >
> > > > > - return true;
> > > > > + return cmo;
> > > >
> > > > I don't really understand the changes that you are making to this
> > > > function, so that is tries really hard to call
> > > > riscv_noncoherent_supported(). Why do we need to always call the function
> > > > in the erratum's probe function, if the erratum is not detected, given
> > >
> > > In one unified kernel Image, to support both coherent and noncoherent
> > > platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
> > > kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.
> >
> > seems adding three words can make it better:
> >
> > kmalloc meet both cases at the beginning, specifically ...
> >
> > > Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
> > > ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
> > > to 1. The notice action is done in patch 5:
> > >
> > > + } else {
> > > + dma_cache_alignment = 1;
> > >
> > >
> > > > that riscv_noncoherent_supported() is called immediately after
> > > > apply_boot_alternatives() in setup_arch()?
>
> This bit here is the key part of my confusion. You try really hard in
> the errata stuff to call riscv_noncoherent_supported(), which I do
> understand is because of the other branch that you add to the function
> later in the series.
>
> What I do not understand is why we are not able to rely on the call to
> it in setup_arch() to trigger it when we do not have T-HEAD CMOs or
> Zicbom.
> You've explained why you want to make sure it always gets called during
> boot, but my question is about why it looks like it is being called more
> than once.
>
> Actually, now that I think of it, what happens on a T-HEAD system where
> there is no T-HEAD CMOs, but there is Zicbom. In theory, this could
> exist.
> Bear with me here a moment in case I am completely wrong, snippet is
> from setup_arch()
> apply_boot_alternatives();
> On my example system, this will trigger, eventually sending us into
> errata_probe_cmo(), where we will call riscv_noncoherent_supported()
> with false, setting dma_cache_alignment to 1.
>
> if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> riscv_isa_extension_available(NULL, ZICBOM))
> cmo = true;
>
> On this system, this will be true.
>
> else
> cmo = false;
> riscv_noncoherent_supported(cmo);
>
> now riscv_noncoherent_supported() is called with true, and we have
> dma_cache_alignment = 1 still. Is that not problematic? Or the inverse,
> where the T-HEAD system has its custom CMOs and there is no Zicbom, it
> gets called twice with different args too.
>
Thank you Conor. You pointed out a bug in my series. It looks like we
need to defer the dma_cache_alignment modification a bit until T-HEAD
CMO probing is done, but we also need to think carefully about T-HEAD
related CONFIG option is disabled. I will take care this case in v2
once Catalin's series is merged.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
` (3 preceding siblings ...)
2023-05-26 16:59 ` [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
2023-05-29 11:17 ` Conor Dooley
2023-05-26 16:59 ` [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Jisheng Zhang
5 siblings, 1 reply; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E
64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel
Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus
it brings some bad effects to for coherent platforms:
Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and
kmalloc-8 slab caches don't exist any more, they are replaced with
either kmalloc-128 or kmalloc-64.
Secondly, larger than necessary kmalloc aligned allocations results
in unnecessary cache/TLB pressure.
This issue also exists on arm64 platforms. From last year, Catalin
tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from
ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to
dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage
in various drivers with ARCH_DMA_MINALIGN etc.
One fact we can make use of for riscv: if the CPU doesn't support
ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on
Catalin's work and above fact, we can easily solve the kmalloc align
issue for riscv: we can override dma_get_cache_alignment(), then let
it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know
the underlying HW neither supports ZICBOM nor supports T-HEAD CMO.
So what about if the CPU supports ZICBOM and T-HEAD CMO, but all the
devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the
kmalloc minimum alignment, nothing changed in this case. This case
can be improved in the future.
After this patch, a simple test of booting to a small buildroot rootfs
on qemu shows:
kmalloc-96 5041 5041 96 ...
kmalloc-64 9606 9606 64 ...
kmalloc-32 5128 5128 32 ...
kmalloc-16 7682 7682 16 ...
kmalloc-8 10246 10246 8 ...
So we save about 1268KB memory. The saving will be much larger in normal
OS env on real HW platforms.
[1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/include/asm/cache.h | 14 ++++++++++++++
arch/riscv/mm/dma-noncoherent.c | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index d3036df23ccb..2174fe7bac9a 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -13,6 +13,7 @@
#ifdef CONFIG_RISCV_DMA_NONCOHERENT
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+#define ARCH_KMALLOC_MINALIGN (8)
#endif
/*
@@ -23,4 +24,17 @@
#define ARCH_SLAB_MINALIGN 16
#endif
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_RISCV_DMA_NONCOHERENT
+extern int dma_cache_alignment;
+#define dma_get_cache_alignment dma_get_cache_alignment
+static inline int dma_get_cache_alignment(void)
+{
+ return dma_cache_alignment;
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
#endif /* _ASM_RISCV_CACHE_H */
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index 0e172e2b4751..21b553c299db 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -11,6 +11,8 @@
#include <asm/cacheflush.h>
static bool noncoherent_supported __ro_after_init;
+int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
+EXPORT_SYMBOL(dma_cache_alignment);
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
enum dma_data_direction dir)
@@ -78,5 +80,7 @@ void riscv_noncoherent_supported(bool cmo)
WARN(!riscv_cbom_block_size,
"Non-coherent DMA support enabled without a block size\n");
noncoherent_supported = true;
+ } else {
+ dma_cache_alignment = 1;
}
}
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-26 16:59 ` [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
@ 2023-05-29 11:17 ` Conor Dooley
2023-05-30 9:59 ` Catalin Marinas
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2023-05-29 11:17 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
linux-kernel, Catalin Marinas
[-- Attachment #1.1: Type: text/plain, Size: 2585 bytes --]
On Sat, May 27, 2023 at 12:59:57AM +0800, Jisheng Zhang wrote:
> Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E
> 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel
> Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus
> it brings some bad effects to for coherent platforms:
>
> Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and
> kmalloc-8 slab caches don't exist any more, they are replaced with
> either kmalloc-128 or kmalloc-64.
>
> Secondly, larger than necessary kmalloc aligned allocations results
> in unnecessary cache/TLB pressure.
>
> This issue also exists on arm64 platforms. From last year, Catalin
> tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from
> ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to
> dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage
> in various drivers with ARCH_DMA_MINALIGN etc.
>
> One fact we can make use of for riscv: if the CPU doesn't support
> ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on
> Catalin's work and above fact, we can easily solve the kmalloc align
> issue for riscv: we can override dma_get_cache_alignment(), then let
> it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know
> the underlying HW neither supports ZICBOM nor supports T-HEAD CMO.
>
> So what about if the CPU supports ZICBOM and T-HEAD CMO, but all the
> devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the
> kmalloc minimum alignment, nothing changed in this case. This case
> can be improved in the future.
>
> After this patch, a simple test of booting to a small buildroot rootfs
> on qemu shows:
>
> kmalloc-96 5041 5041 96 ...
> kmalloc-64 9606 9606 64 ...
> kmalloc-32 5128 5128 32 ...
> kmalloc-16 7682 7682 16 ...
> kmalloc-8 10246 10246 8 ...
>
> So we save about 1268KB memory. The saving will be much larger in normal
> OS env on real HW platforms.
>
> [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Fails to build chief, with loads of:
linux/dma-mapping.h:546:19: error: redefinition of 'dma_get_cache_alignment'
And for 32-bit there's also a rake of:
include/linux/slab.h:239:9: warning: 'ARCH_KMALLOC_MINALIGN' macro redefined [-Wmacro-redefined]
At the very least, reproducable with rv32_defconfig.
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-29 11:17 ` Conor Dooley
@ 2023-05-30 9:59 ` Catalin Marinas
2023-05-30 10:34 ` Conor Dooley
0 siblings, 1 reply; 20+ messages in thread
From: Catalin Marinas @ 2023-05-30 9:59 UTC (permalink / raw)
To: Conor Dooley
Cc: Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel
On Mon, May 29, 2023 at 12:17:46PM +0100, Conor Dooley wrote:
> On Sat, May 27, 2023 at 12:59:57AM +0800, Jisheng Zhang wrote:
> > After this patch, a simple test of booting to a small buildroot rootfs
> > on qemu shows:
> >
> > kmalloc-96 5041 5041 96 ...
> > kmalloc-64 9606 9606 64 ...
> > kmalloc-32 5128 5128 32 ...
> > kmalloc-16 7682 7682 16 ...
> > kmalloc-8 10246 10246 8 ...
> >
> > So we save about 1268KB memory. The saving will be much larger in normal
> > OS env on real HW platforms.
> >
> > [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>
> Fails to build chief, with loads of:
> linux/dma-mapping.h:546:19: error: redefinition of 'dma_get_cache_alignment'
>
> And for 32-bit there's also a rake of:
> include/linux/slab.h:239:9: warning: 'ARCH_KMALLOC_MINALIGN' macro redefined [-Wmacro-redefined]
>
> At the very least, reproducable with rv32_defconfig.
Have you this it on top of the KMALLOC_MINALIGN preparation series?
https://lore.kernel.org/r/20230524171904.3967031-1-catalin.marinas@arm.com/
--
Catalin
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-30 9:59 ` Catalin Marinas
@ 2023-05-30 10:34 ` Conor Dooley
2023-05-30 13:08 ` Catalin Marinas
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2023-05-30 10:34 UTC (permalink / raw)
To: Catalin Marinas
Cc: Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2124 bytes --]
On Tue, May 30, 2023 at 10:59:41AM +0100, Catalin Marinas wrote:
> On Mon, May 29, 2023 at 12:17:46PM +0100, Conor Dooley wrote:
> > On Sat, May 27, 2023 at 12:59:57AM +0800, Jisheng Zhang wrote:
> > > After this patch, a simple test of booting to a small buildroot rootfs
> > > on qemu shows:
> > >
> > > kmalloc-96 5041 5041 96 ...
> > > kmalloc-64 9606 9606 64 ...
> > > kmalloc-32 5128 5128 32 ...
> > > kmalloc-16 7682 7682 16 ...
> > > kmalloc-8 10246 10246 8 ...
> > >
> > > So we save about 1268KB memory. The saving will be much larger in normal
> > > OS env on real HW platforms.
> > >
> > > [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
While I think of it, Link: goes at the start of the line, the [1] should
go at the end (although I don't think you actually reference the link
anywhere in the text & it'll probably not be particularly relevant if a
subsequent revision of that patchset is applied.
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> >
> > Fails to build chief, with loads of:
> > linux/dma-mapping.h:546:19: error: redefinition of 'dma_get_cache_alignment'
> >
> > And for 32-bit there's also a rake of:
> > include/linux/slab.h:239:9: warning: 'ARCH_KMALLOC_MINALIGN' macro redefined [-Wmacro-redefined]
> >
> > At the very least, reproducable with rv32_defconfig.
>
> Have you this it on top of the KMALLOC_MINALIGN preparation series?
>
> https://lore.kernel.org/r/20230524171904.3967031-1-catalin.marinas@arm.com/
Oh, no. Thanks for pointing that out.
Our automation stuff only uses what is in riscv/{for-next,master,fixes}.
Unless my reading comprehension is particularly bad of late it was
non-obvious that this depended on something that had not yet been
applied - it sounded like your series had already been merged last year.
Apologies for the noise then on this patch, but please try to be more
clear about what the dependencies actually are Jisheng.
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-30 10:34 ` Conor Dooley
@ 2023-05-30 13:08 ` Catalin Marinas
2023-05-31 14:52 ` Jisheng Zhang
0 siblings, 1 reply; 20+ messages in thread
From: Catalin Marinas @ 2023-05-30 13:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Jisheng Zhang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel
On Tue, May 30, 2023 at 11:34:06AM +0100, Conor Dooley wrote:
> On Tue, May 30, 2023 at 10:59:41AM +0100, Catalin Marinas wrote:
> > On Mon, May 29, 2023 at 12:17:46PM +0100, Conor Dooley wrote:
> > > On Sat, May 27, 2023 at 12:59:57AM +0800, Jisheng Zhang wrote:
> > > > After this patch, a simple test of booting to a small buildroot rootfs
> > > > on qemu shows:
> > > >
> > > > kmalloc-96 5041 5041 96 ...
> > > > kmalloc-64 9606 9606 64 ...
> > > > kmalloc-32 5128 5128 32 ...
> > > > kmalloc-16 7682 7682 16 ...
> > > > kmalloc-8 10246 10246 8 ...
> > > >
> > > > So we save about 1268KB memory. The saving will be much larger in normal
> > > > OS env on real HW platforms.
> > > >
> > > > [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
>
> While I think of it, Link: goes at the start of the line, the [1] should
> go at the end (although I don't think you actually reference the link
> anywhere in the text & it'll probably not be particularly relevant if a
> subsequent revision of that patchset is applied.
I plan to post at least one more. I'd suggest the risc-v patchset to
only go in once my series landed.
> > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > >
> > > Fails to build chief, with loads of:
> > > linux/dma-mapping.h:546:19: error: redefinition of 'dma_get_cache_alignment'
> > >
> > > And for 32-bit there's also a rake of:
> > > include/linux/slab.h:239:9: warning: 'ARCH_KMALLOC_MINALIGN' macro redefined [-Wmacro-redefined]
> > >
> > > At the very least, reproducable with rv32_defconfig.
> >
> > Have you this it on top of the KMALLOC_MINALIGN preparation series?
> >
> > https://lore.kernel.org/r/20230524171904.3967031-1-catalin.marinas@arm.com/
>
> Oh, no. Thanks for pointing that out.
> Our automation stuff only uses what is in riscv/{for-next,master,fixes}.
> Unless my reading comprehension is particularly bad of late it was
> non-obvious that this depended on something that had not yet been
> applied - it sounded like your series had already been merged last year.
Yeah, it was only obvious to me since it was my series ;).
--
Catalin
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value
2023-05-30 13:08 ` Catalin Marinas
@ 2023-05-31 14:52 ` Jisheng Zhang
0 siblings, 0 replies; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-31 14:52 UTC (permalink / raw)
To: Catalin Marinas
Cc: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
linux-riscv, linux-kernel
On Tue, May 30, 2023 at 02:08:10PM +0100, Catalin Marinas wrote:
> On Tue, May 30, 2023 at 11:34:06AM +0100, Conor Dooley wrote:
> > On Tue, May 30, 2023 at 10:59:41AM +0100, Catalin Marinas wrote:
> > > On Mon, May 29, 2023 at 12:17:46PM +0100, Conor Dooley wrote:
> > > > On Sat, May 27, 2023 at 12:59:57AM +0800, Jisheng Zhang wrote:
> > > > > After this patch, a simple test of booting to a small buildroot rootfs
> > > > > on qemu shows:
> > > > >
> > > > > kmalloc-96 5041 5041 96 ...
> > > > > kmalloc-64 9606 9606 64 ...
> > > > > kmalloc-32 5128 5128 32 ...
> > > > > kmalloc-16 7682 7682 16 ...
> > > > > kmalloc-8 10246 10246 8 ...
> > > > >
> > > > > So we save about 1268KB memory. The saving will be much larger in normal
> > > > > OS env on real HW platforms.
> > > > >
> > > > > [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
> >
> > While I think of it, Link: goes at the start of the line, the [1] should
> > go at the end (although I don't think you actually reference the link
> > anywhere in the text & it'll probably not be particularly relevant if a
> > subsequent revision of that patchset is applied.
>
> I plan to post at least one more. I'd suggest the risc-v patchset to
> only go in once my series landed.
Sure I will wait for your series landing in linus tree firstly.
>
> > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > >
> > > > Fails to build chief, with loads of:
> > > > linux/dma-mapping.h:546:19: error: redefinition of 'dma_get_cache_alignment'
> > > >
> > > > And for 32-bit there's also a rake of:
> > > > include/linux/slab.h:239:9: warning: 'ARCH_KMALLOC_MINALIGN' macro redefined [-Wmacro-redefined]
> > > >
> > > > At the very least, reproducable with rv32_defconfig.
> > >
> > > Have you this it on top of the KMALLOC_MINALIGN preparation series?
> > >
> > > https://lore.kernel.org/r/20230524171904.3967031-1-catalin.marinas@arm.com/
> >
> > Oh, no. Thanks for pointing that out.
> > Our automation stuff only uses what is in riscv/{for-next,master,fixes}.
> > Unless my reading comprehension is particularly bad of late it was
Aha I dunno this mechanism before.
> > non-obvious that this depended on something that had not yet been
Your reading comprehension is good ;) I just listed the dependency but
didn't explictly mention its merge status.
I will wait for Catalin's series being merged.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
` (4 preceding siblings ...)
2023-05-26 16:59 ` [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
@ 2023-05-26 16:59 ` Jisheng Zhang
5 siblings, 0 replies; 20+ messages in thread
From: Jisheng Zhang @ 2023-05-26 16:59 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, linux-kernel, Catalin Marinas
With the DMA bouncing of unaligned kmalloc() buffers now in place,
enable it for riscv when RISCV_DMA_NONCOHERENT=y to allow the
kmalloc-{8,16,32,96} caches. Since RV32 doesn't enable SWIOTLB
yet, and I didn't see any dma noncoherent RV32 platforms in the
mainline, so skip RV32 now by only enabling
DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB is available. Once we see
such requirement on RV32, we can enable it then.
NOTE: we didn't force to create the swiotlb buffer even when the
end of RAM is within the 32-bit physical address range. That's to
say:
For RV64 with > 4GB memory, the feature is enabled.
For RV64 with <= 4GB memory, the feature isn't enabled by default. We
rely on users to pass "swiotlb=mmnn,force" where mmnn is the Number of
I/O TLB slabs, see kernel-parameters.txt for details.
Tested on Sipeed Lichee Pi 4A with 8GB DDR and Sipeed M1S BL808 Dock
board.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b958f67f9a12..14f030cd6357 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -260,6 +260,7 @@ config RISCV_DMA_NONCOHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select DMA_DIRECT_REMAP
+ select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
config AS_HAS_INSN
def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
--
2.40.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread