[PATCH v7 00/16] Support Andes PMU extension

[PATCH v7 00/16] Support Andes PMU extension

[Yu Chien Peter Lin]

Hi All,

This patch series introduces the Andes PMU extension, which serves
the same purpose as Sscofpmf. To use FDT-based probing for hardware
support of the PMU extensions and introduce Andes PMU alternatives,
we first convert T-Head's PMU to CPU feature alternative.

Its non-standard local interrupt is assigned to bit 18 in the
custom S-mode local interrupt enable/pending registers (slie/slip),
while the interrupt cause is (256 + 18).

Linux patches based on:
- ed5b7cf ("riscv: errata: andes: Probe for IOCP only once in boot stage")
It can be found on Andes Technology GitHub:
- https://github.com/andestech/linux/commits/andes-pmu-support-v7

The PMU device tree node used on AX45MP:
- https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3

Locus Wei-Han Chen (1):
  riscv: andes: Support specifying symbolic firmware and hardware raw
    events

Yu Chien Peter Lin (15):
  riscv: errata: Rename defines for Andes
  irqchip/riscv-intc: Allow large non-standard interrupt number
  irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  dt-bindings: riscv: Add Andes interrupt controller compatible string
  riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
    INTC
  perf: RISC-V: Eliminate redundant interrupt enable/disable operations
  RISC-V: Move T-Head PMU to CPU feature alternative framework
  perf: RISC-V: Introduce Andes PMU for perf event sampling
  dt-bindings: riscv: Add T-Head PMU extension description
  dt-bindings: riscv: Add Andes PMU extension description
  riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s
  riscv: dts: sophgo: Add T-Head PMU extension for cv1800b
  riscv: dts: sophgo: Add T-Head PMU extension for sg2042
  riscv: dts: thead: Add T-Head PMU extension for th1520
  riscv: dts: renesas: Add Andes PMU extension for r9a07g043f

 .../devicetree/bindings/riscv/cpus.yaml       |   6 +-
 .../devicetree/bindings/riscv/extensions.yaml |  13 ++
 arch/riscv/Kconfig.errata                     |  13 --
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi |   2 +-
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |   4 +-
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi       |   2 +-
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 128 +++++++++---------
 arch/riscv/boot/dts/thead/th1520.dtsi         |   8 +-
 arch/riscv/errata/andes/errata.c              |  10 +-
 arch/riscv/errata/thead/errata.c              |  19 ---
 arch/riscv/include/asm/errata_list.h          |  19 +--
 arch/riscv/include/asm/hwcap.h                |   2 +
 arch/riscv/include/asm/vendorid_list.h        |   2 +-
 arch/riscv/kernel/alternative.c               |   2 +-
 arch/riscv/kernel/cpufeature.c                |   2 +
 drivers/irqchip/irq-riscv-intc.c              |  88 ++++++++++--
 drivers/perf/Kconfig                          |  27 ++++
 drivers/perf/riscv_pmu_sbi.c                  |  47 +++++--
 include/linux/soc/andes/irq.h                 |  18 +++
 .../arch/riscv/andes/ax45/firmware.json       |  68 ++++++++++
 .../arch/riscv/andes/ax45/instructions.json   | 127 +++++++++++++++++
 .../arch/riscv/andes/ax45/memory.json         |  57 ++++++++
 .../arch/riscv/andes/ax45/microarch.json      |  77 +++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |   1 +
 24 files changed, 591 insertions(+), 151 deletions(-)
 create mode 100644 include/linux/soc/andes/irq.h
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json

-- 
2.34.1


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[PATCH v7 01/16] riscv: errata: Rename defines for Andes

[Yu Chien Peter Lin]

Use "ANDES" rather than "ANDESTECH" to unify the naming
convention with directory, file names, Kconfig options
and other definitions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
  - No change
Changes v2 -> v3:
  - Rewrite commit message (suggested by Conor)
Changes v3 -> v4:
  - Include Conor's Acked-by tag
Changes v4 -> v5:
  - Include Prabhakar's RB tag
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 arch/riscv/errata/andes/errata.c       | 10 +++++-----
 arch/riscv/include/asm/errata_list.h   |  4 ++--
 arch/riscv/include/asm/vendorid_list.h |  2 +-
 arch/riscv/kernel/alternative.c        |  2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 17a904869724..f2708a9494a1 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -18,9 +18,9 @@
 #include <asm/sbi.h>
 #include <asm/vendorid_list.h>
 
-#define ANDESTECH_AX45MP_MARCHID	0x8000000000008a45UL
-#define ANDESTECH_AX45MP_MIMPID		0x500UL
-#define ANDESTECH_SBI_EXT_ANDES		0x0900031E
+#define ANDES_AX45MP_MARCHID		0x8000000000008a45UL
+#define ANDES_AX45MP_MIMPID		0x500UL
+#define ANDES_SBI_EXT_ANDES		0x0900031E
 
 #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
 
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
 	 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
 	 * cache is controllable only then CMO will be applied to the platform.
 	 */
-	ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
+	ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
 			0, 0, 0, 0, 0, 0);
 
 	return ret.error ? 0 : ret.value;
@@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
 
 	done = true;
 
-	if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
+	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
 		return;
 
 	if (!ax45mp_iocp_sw_workaround())
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 83ed25e43553..4ed21a62158c 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -12,8 +12,8 @@
 #include <asm/vendorid_list.h>
 
 #ifdef CONFIG_ERRATA_ANDES
-#define ERRATA_ANDESTECH_NO_IOCP	0
-#define ERRATA_ANDESTECH_NUMBER		1
+#define ERRATA_ANDES_NO_IOCP 0
+#define ERRATA_ANDES_NUMBER 1
 #endif
 
 #ifdef CONFIG_ERRATA_SIFIVE
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index e55407ace0c3..2f2bb0c84f9a 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,7 +5,7 @@
 #ifndef ASM_VENDOR_LIST_H
 #define ASM_VENDOR_LIST_H
 
-#define ANDESTECH_VENDOR_ID	0x31e
+#define ANDES_VENDOR_ID		0x31e
 #define SIFIVE_VENDOR_ID	0x489
 #define THEAD_VENDOR_ID		0x5b7
 
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 319a1da0358b..0128b161bfda 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
 
 	switch (cpu_mfr_info->vendor_id) {
 #ifdef CONFIG_ERRATA_ANDES
-	case ANDESTECH_VENDOR_ID:
+	case ANDES_VENDOR_ID:
 		cpu_mfr_info->patch_func = andes_errata_patch_func;
 		break;
 #endif
-- 
2.34.1


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[PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number

[Yu Chien Peter Lin]

Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.

To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
---
Changes v1 -> v2:
  - Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
  - No change
Changes v3 -> v4: (Suggested by Thomas [1])
  - Use pr_warn_ratelimited instead
  - Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
  - Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
  - Add riscv_intc_* global variables for checking range in riscv_intc_domain_alloc()
  - Advertise the number of interrupts allowed
Changes v6 -> v7:
  - No functional change

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
[2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
---
 drivers/irqchip/irq-riscv-intc.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..b13a16b164c9 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,17 @@
 #include <linux/smp.h>
 
 static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init;
+static unsigned int riscv_intc_custom_base __ro_after_init;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
 
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-	if (unlikely(cause >= BITS_PER_LONG))
-		panic("unexpected interrupt cause");
-
-	generic_handle_domain_irq(intc_domain, cause);
+	if (generic_handle_domain_irq(intc_domain, cause))
+		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
+				    cause);
 }
 
 /*
@@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
 	if (ret)
 		return ret;
 
+	/*
+	 * Only allow hwirq for which we have corresponding standard or
+	 * custom interrupt enable register.
+	 */
+	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
+	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
+		return -EINVAL;
+
 	for (i = 0; i < nr_irqs; i++) {
 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
 		if (ret)
@@ -117,8 +127,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-					       &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -132,7 +141,10 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+	if (riscv_intc_custom_nr_irqs)
+		pr_info("%d custom local interrupts mapped\n",
+			riscv_intc_custom_nr_irqs);
 
 	return 0;
 }
@@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
+	riscv_intc_nr_irqs = BITS_PER_LONG;
+	riscv_intc_custom_base = riscv_intc_nr_irqs;
+	riscv_intc_custom_nr_irqs = 0;
+
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }
 
-- 
2.34.1


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[PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

[Yu Chien Peter Lin]

Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.

To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.

Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,

  cpu0: cpu@0 {
      compatible = "andestech,ax45mp", "riscv";
      ...
      cpu0-intc: interrupt-controller {
          #interrupt-cells = <0x01>;
          compatible = "andestech,cpu-intc", "riscv,cpu-intc";
          interrupt-controller;
      };
  };

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Return -ENXIO if no valid compatible INTC found
  - Allow falling back to generic RISC-V INTC
Changes v3 -> v4: (Suggested by Thomas [1])
  - Add comment to andes irq chip function
  - Refine code flow to share with generic RISC-V INTC and ACPI
  - Move Andes specific definitions to include/linux/soc/andes/irq.h
Changes v4 -> v5: (Suggested by Thomas)
  - Fix commit message
  - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
  - Do not set chip_data to the chip itself with irq_domain_set_info()
  - Follow reverse fir tree order variable declarations
Changes v5 -> v6:
  - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI
  - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup)
  - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32)
Changes v6 -> v7:
  - No change

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
---
 drivers/irqchip/irq-riscv-intc.c | 66 +++++++++++++++++++++++++++-----
 include/linux/soc/andes/irq.h    | 18 +++++++++
 2 files changed, 74 insertions(+), 10 deletions(-)
 create mode 100644 include/linux/soc/andes/irq.h

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index b13a16b164c9..7064857f1f1d 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
 
 static struct irq_domain *intc_domain;
 static unsigned int riscv_intc_nr_irqs __ro_after_init;
@@ -49,6 +50,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
 	csr_set(CSR_IE, BIT(d->hwirq));
 }
 
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+	/*
+	 * Andes specific S-mode local interrupt causes (hwirq)
+	 * are defined as (256 + n) and controlled by n-th bit
+	 * of SLIE.
+	 */
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_clear(CSR_IE, mask);
+	else
+		csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_set(CSR_IE, mask);
+	else
+		csr_set(ANDES_CSR_SLIE, mask);
+}
+
 static void riscv_intc_irq_eoi(struct irq_data *d)
 {
 	/*
@@ -72,12 +98,21 @@ static struct irq_chip riscv_intc_chip = {
 	.irq_eoi = riscv_intc_irq_eoi,
 };
 
+static struct irq_chip andes_intc_chip = {
+	.name		= "RISC-V INTC",
+	.irq_mask	= andes_intc_irq_mask,
+	.irq_unmask	= andes_intc_irq_unmask,
+	.irq_eoi	= riscv_intc_irq_eoi,
+};
+
 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
 				 irq_hw_number_t hwirq)
 {
+	struct irq_chip *chip = d->host_data;
+
 	irq_set_percpu_devid(irq);
-	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
-			    handle_percpu_devid_irq, NULL, NULL);
+	irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
+			    NULL, NULL);
 
 	return 0;
 }
@@ -123,11 +158,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
 	return intc_domain->fwnode;
 }
 
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+					 struct irq_chip *chip)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 static int __init riscv_intc_init(struct device_node *node,
 				  struct device_node *parent)
 {
-	int rc;
+	struct irq_chip *chip;
 	unsigned long hartid;
+	int rc;
 
 	rc = riscv_of_parent_hartid(node, &hartid);
 	if (rc < 0) {
@@ -178,14 +215,23 @@ static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
-	riscv_intc_nr_irqs = BITS_PER_LONG;
-	riscv_intc_custom_base = riscv_intc_nr_irqs;
-	riscv_intc_custom_nr_irqs = 0;
+	if (of_device_is_compatible(node, "andestech,cpu-intc")) {
+		riscv_intc_nr_irqs = BITS_PER_LONG;
+		riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
+		riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
+		chip = &andes_intc_chip;
+	} else {
+		riscv_intc_nr_irqs = BITS_PER_LONG;
+		riscv_intc_custom_base = riscv_intc_nr_irqs;
+		riscv_intc_custom_nr_irqs = 0;
+		chip = &riscv_intc_chip;
+	}
 
-	return riscv_intc_init_common(of_node_to_fwnode(node));
+	return riscv_intc_init_common(of_node_to_fwnode(node), chip);
 }
 
 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
 
 #ifdef CONFIG_ACPI
 
@@ -212,7 +258,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
 		return -ENOMEM;
 	}
 
-	return riscv_intc_init_common(fn);
+	return riscv_intc_init_common(fn, &riscv_intc_chip);
 }
 
 IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..edc3182d6e66
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMOVI		18
+#define ANDES_RV_IRQ_LAST		ANDES_RV_IRQ_PMOVI
+#define ANDES_SLI_CAUSE_BASE		256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE			0x9c4
+#define ANDES_CSR_SLIP			0x9c5
+#define ANDES_CSR_SCOUNTEROF		0x9d4
+
+#endif /* __ANDES_IRQ_H */
-- 
2.34.1


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[PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string

[Yu Chien Peter Lin]

Add "andestech,cpu-intc" compatible string to indicate that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
which can be handled in supervisor mode:

- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt

These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Updated commit message
  - Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
  - Add const entry instead of enum (Suggested by Conor)
Changes v4 -> v5:
  - Include Conor's Acked-by
  - Include Prabhakar's Reviewed-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 23646b684ea2..33c2b620a59f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -101,7 +101,11 @@ properties:
         const: 1
 
       compatible:
-        const: riscv,cpu-intc
+        oneOf:
+          - items:
+              - const: andestech,cpu-intc
+              - const: riscv,cpu-intc
+          - const: riscv,cpu-intc
 
       interrupt-controller: true
 
-- 
2.34.1


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[PATCH v7 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC

[Yu Chien Peter Lin]

The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Geert's Reviewed-by
  - Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index a92cfcfc021b..099f3df75b42 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -39,7 +39,7 @@ cpu0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
 				interrupt-controller;
 			};
 		};
-- 
2.34.1


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[PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations

[Yu Chien Peter Lin]

The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). It can be done only once.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
in the initial PATCH3 [1].

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/

Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - No change
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - No change
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 drivers/perf/riscv_pmu_sbi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 16acd4dcdb96..2edbc37abadf 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
 	if (riscv_pmu_use_irq) {
 		cpu_hw_evt->irq = riscv_pmu_irq;
 		csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
-		csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
 		enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
 	}
 
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
 {
 	if (riscv_pmu_use_irq) {
 		disable_percpu_irq(riscv_pmu_irq);
-		csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
 	}
 
 	/* Disable all counters access for user mode now */
-- 
2.34.1


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[PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Yu Chien Peter Lin]

The custom PMU extension aims to support perf event sampling prior
to the ratification of Sscofpmf. Instead of diverting the bits and
register reserved for future standard, a set of custom registers is
added.  Hence, we may consider it as a CPU feature rather than an
erratum.

T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
for proper functioning as of this commit.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Guo's Reviewed-by
  - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
Changes v5 -> v6:
  - Include Conor's Reviewed-by
Changes v6 -> v7:
  - No change
---
 arch/riscv/Kconfig.errata            | 13 -------------
 arch/riscv/errata/thead/errata.c     | 19 -------------------
 arch/riscv/include/asm/errata_list.h | 15 +--------------
 arch/riscv/include/asm/hwcap.h       |  1 +
 arch/riscv/kernel/cpufeature.c       |  1 +
 drivers/perf/Kconfig                 | 13 +++++++++++++
 drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
 7 files changed, 30 insertions(+), 51 deletions(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e2c731cfed8c..0d19f47d1018 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
 
 	  If you don't know what to do here, say "Y".
 
-config ERRATA_THEAD_PMU
-	bool "Apply T-Head PMU errata"
-	depends on ERRATA_THEAD && RISCV_PMU_SBI
-	default y
-	help
-	  The T-Head C9xx cores implement a PMU overflow extension very
-	  similar to the core SSCOFPMF extension.
-
-	  This will apply the overflow errata to handle the non-standard
-	  behaviour via the regular SBI PMU driver and interface.
-
-	  If you don't know what to do here, say "Y".
-
 endmenu # "CPU errata selection"
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 0554ed4bf087..5de5f7209132 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
 	return true;
 }
 
-static bool errata_probe_pmu(unsigned int stage,
-			     unsigned long arch_id, unsigned long impid)
-{
-	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
-		return false;
-
-	/* target-c9xx cores report arch_id and impid as 0 */
-	if (arch_id != 0 || impid != 0)
-		return false;
-
-	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
-		return false;
-
-	return true;
-}
-
 static u32 thead_errata_probe(unsigned int stage,
 			      unsigned long archid, unsigned long impid)
 {
@@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
 	if (errata_probe_cmo(stage, archid, impid))
 		cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
 
-	if (errata_probe_pmu(stage, archid, impid))
-		cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
-
 	return cpu_req_errata;
 }
 
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 4ed21a62158c..9bccc2ba0eb5 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -25,8 +25,7 @@
 #ifdef CONFIG_ERRATA_THEAD
 #define	ERRATA_THEAD_PBMT 0
 #define	ERRATA_THEAD_CMO 1
-#define	ERRATA_THEAD_PMU 2
-#define	ERRATA_THEAD_NUMBER 3
+#define	ERRATA_THEAD_NUMBER 2
 #endif
 
 #ifdef __ASSEMBLY__
@@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(						\
 	    "r"((unsigned long)(_start) + (_size))			\
 	: "a0")
 
-#define THEAD_C9XX_RV_IRQ_PMU			17
-#define THEAD_C9XX_CSR_SCOUNTEROF		0x5c5
-
-#define ALT_SBI_PMU_OVERFLOW(__ovl)					\
-asm volatile(ALTERNATIVE(						\
-	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\
-	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\
-		THEAD_VENDOR_ID, ERRATA_THEAD_PMU,			\
-		CONFIG_ERRATA_THEAD_PMU)				\
-	: "=r" (__ovl) :						\
-	: "memory")
-
 #endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5340f818746b..480f9da7fba7 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -80,6 +80,7 @@
 #define RISCV_ISA_EXT_ZFA		71
 #define RISCV_ISA_EXT_ZTSO		72
 #define RISCV_ISA_EXT_ZACAS		73
+#define RISCV_ISA_EXT_XTHEADPMU		74
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e32591e9da90..4aded5bf8fc3 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+	__RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
 };
 
 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 273d67ecf6d2..6cef15ec7c25 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -86,6 +86,19 @@ config RISCV_PMU_SBI
 	  full perf feature support i.e. counter overflow, privilege mode
 	  filtering, counter configuration.
 
+config THEAD_CUSTOM_PMU
+	bool "T-Head custom PMU support"
+	depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+	default y
+	help
+	  The T-Head C9xx cores implement a PMU overflow extension very
+	  similar to the core SSCOFPMF extension.
+
+	  This will patch the overflow CSR and handle the non-standard
+	  behaviour via the regular SBI PMU driver and interface.
+
+	  If you don't know what to do here, say "Y".
+
 config ARM_PMU_ACPI
 	depends on ARM_PMU && ACPI
 	def_bool y
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 2edbc37abadf..31ca79846399 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -20,10 +20,21 @@
 #include <linux/cpu_pm.h>
 #include <linux/sched/clock.h>
 
-#include <asm/errata_list.h>
 #include <asm/sbi.h>
 #include <asm/cpufeature.h>
 
+#define THEAD_C9XX_RV_IRQ_PMU		17
+#define THEAD_C9XX_CSR_SCOUNTEROF	0x5c5
+
+#define ALT_SBI_PMU_OVERFLOW(__ovl)					\
+asm volatile(ALTERNATIVE(						\
+	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\
+	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\
+		0, RISCV_ISA_EXT_XTHEADPMU,				\
+		CONFIG_THEAD_CUSTOM_PMU)				\
+	: "=r" (__ovl) :						\
+	: "memory")
+
 #define SYSCTL_NO_USER_ACCESS	0
 #define SYSCTL_USER_ACCESS	1
 #define SYSCTL_LEGACY		2
@@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
 	if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
 		riscv_pmu_irq_num = RV_IRQ_PMU;
 		riscv_pmu_use_irq = true;
-	} else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
-		   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
-		   riscv_cached_marchid(0) == 0 &&
-		   riscv_cached_mimpid(0) == 0) {
+	} else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
+		   IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
 		riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
 		riscv_pmu_use_irq = true;
 	}
-- 
2.34.1


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[PATCH v7 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling

[Yu Chien Peter Lin]

The Andes PMU extension provides the same mechanism as Sscofpmf,
allowing us to reuse the SBI PMU driver to support event sampling
and mode filtering.

To make use of this custom PMU extension, "xandespmu" needs
to be appended to the riscv,isa-extensions for each cpu node
in device-tree, and enable CONFIG_ANDES_CUSTOM_PMU.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Co-developed-by: Locus Wei-Han Chen <locus84@andestech.com>
Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Reordered list in riscv_isa_ext[]
  - Removed mvendorid check in pmu_sbi_setup_irqs()
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Let ANDES_CUSTOM_PMU depend on ARCH_RENESAS
  - Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 arch/riscv/include/asm/hwcap.h |  1 +
 arch/riscv/kernel/cpufeature.c |  1 +
 drivers/perf/Kconfig           | 14 ++++++++++++++
 drivers/perf/riscv_pmu_sbi.c   | 30 +++++++++++++++++++++++++-----
 4 files changed, 41 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 480f9da7fba7..c77da1c9f32b 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -81,6 +81,7 @@
 #define RISCV_ISA_EXT_ZTSO		72
 #define RISCV_ISA_EXT_ZACAS		73
 #define RISCV_ISA_EXT_XTHEADPMU		74
+#define RISCV_ISA_EXT_XANDESPMU		75
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 4aded5bf8fc3..bdf8d2be3ea6 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
 	__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
 	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+	__RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU),
 	__RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
 };
 
diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
index 6cef15ec7c25..18f4c62eafc2 100644
--- a/drivers/perf/Kconfig
+++ b/drivers/perf/Kconfig
@@ -86,6 +86,20 @@ config RISCV_PMU_SBI
 	  full perf feature support i.e. counter overflow, privilege mode
 	  filtering, counter configuration.
 
+config ANDES_CUSTOM_PMU
+	bool "Andes custom PMU support"
+	depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI
+	default y
+	help
+	  The Andes cores implement a PMU overflow extension very
+	  similar to the core SSCOFPMF extension.
+
+	  This will patch the overflow/pending CSR and handle the
+	  non-standard behaviour via the regular SBI PMU driver and
+	  interface.
+
+	  If you don't know what to do here, say "Y".
+
 config THEAD_CUSTOM_PMU
 	bool "T-Head custom PMU support"
 	depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 31ca79846399..4d5d478430c8 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -19,6 +19,7 @@
 #include <linux/of.h>
 #include <linux/cpu_pm.h>
 #include <linux/sched/clock.h>
+#include <linux/soc/andes/irq.h>
 
 #include <asm/sbi.h>
 #include <asm/cpufeature.h>
@@ -27,14 +28,26 @@
 #define THEAD_C9XX_CSR_SCOUNTEROF	0x5c5
 
 #define ALT_SBI_PMU_OVERFLOW(__ovl)					\
-asm volatile(ALTERNATIVE(						\
+asm volatile(ALTERNATIVE_2(						\
 	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\
 	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\
 		0, RISCV_ISA_EXT_XTHEADPMU,				\
-		CONFIG_THEAD_CUSTOM_PMU)				\
+		CONFIG_THEAD_CUSTOM_PMU,				\
+	"csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF),			\
+		0, RISCV_ISA_EXT_XANDESPMU,		\
+		CONFIG_ANDES_CUSTOM_PMU)				\
 	: "=r" (__ovl) :						\
 	: "memory")
 
+#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask)			\
+asm volatile(ALTERNATIVE(						\
+	"csrc " __stringify(CSR_IP) ", %0\n\t",				\
+	"csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t",			\
+		0, RISCV_ISA_EXT_XANDESPMU,				\
+		CONFIG_ANDES_CUSTOM_PMU)				\
+	: : "r"(__irq_mask)						\
+	: "memory")
+
 #define SYSCTL_NO_USER_ACCESS	0
 #define SYSCTL_USER_ACCESS	1
 #define SYSCTL_LEGACY		2
@@ -72,6 +85,7 @@ static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS;
 static union sbi_pmu_ctr_info *pmu_ctr_list;
 static bool riscv_pmu_use_irq;
 static unsigned int riscv_pmu_irq_num;
+static unsigned int riscv_pmu_irq_mask;
 static unsigned int riscv_pmu_irq;
 
 /* Cache the available counters in a bitmask */
@@ -705,7 +719,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
 
 	event = cpu_hw_evt->events[fidx];
 	if (!event) {
-		csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
+		ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
 		return IRQ_NONE;
 	}
 
@@ -719,7 +733,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev)
 	 * Overflow interrupt pending bit should only be cleared after stopping
 	 * all the counters to avoid any race condition.
 	 */
-	csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num));
+	ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
 
 	/* No overflow bit is set */
 	if (!overflow)
@@ -791,7 +805,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
 
 	if (riscv_pmu_use_irq) {
 		cpu_hw_evt->irq = riscv_pmu_irq;
-		csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
+		ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask);
 		enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
 	}
 
@@ -823,8 +837,14 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
 		   IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
 		riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
 		riscv_pmu_use_irq = true;
+	} else if (riscv_isa_extension_available(NULL, XANDESPMU) &&
+		   IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) {
+		riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI;
+		riscv_pmu_use_irq = true;
 	}
 
+	riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
+
 	if (!riscv_pmu_use_irq)
 		return -EOPNOTSUPP;
 
-- 
2.34.1


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[PATCH v7 09/16] dt-bindings: riscv: Add T-Head PMU extension description

[Yu Chien Peter Lin]

Document the ISA string for T-Head performance monitor extension
which provides counter overflow interrupt mechanism.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v2 -> v3:
  - New patch
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Guo's Reviewed-by
  - Include Inochi's Reviewed-by
  - Update to C910 documentation with its commit hash
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 27beedb98198..ee0747f29d6d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,11 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        - const: xtheadpmu
+          description:
+            The T-Head performance monitor extension for counter overflow, as ratified
+            in commit 4c4981 ("Initial commit") of Xuantie C910 user manual.
+            https://github.com/T-head-Semi/openc910/tree/main/doc
+
 additionalProperties: true
 ...
-- 
2.34.1


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[PATCH v7 10/16] dt-bindings: riscv: Add Andes PMU extension description

[Yu Chien Peter Lin]

Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v2 -> v3:
  - New patch
Changes v3 -> v4:
  - Include Conor's Acked-by
Changes v4 -> v5:
  - Include Prabhakar's Reviewed-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ee0747f29d6d..ecc7a105e7fc 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,6 +477,13 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        - const: xandespmu
+          description:
+            The Andes Technology performance monitor extension for counter overflow
+            and privilege mode filtering. For more details, see Counter Related
+            Registers in the AX45MP datasheet.
+            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
         - const: xtheadpmu
           description:
             The T-Head performance monitor extension for counter overflow, as ratified
-- 
2.34.1


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[PATCH v7 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s

[Yu Chien Peter Lin]

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
Changes v2 -> v3:
  - New patch
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Guo's Reviewed-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..7dcba86cfdd0 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {
-- 
2.34.1


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[PATCH v7 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b

[Yu Chien Peter Lin]

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v4 -> v5:
  - New patch
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..74655ea45b28 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -29,7 +29,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
-- 
2.34.1


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[PATCH v7 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042

[Yu Chien Peter Lin]

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v4 -> v5:
  - New patch
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
 1 file changed, 64 insertions(+), 64 deletions(-)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index b136b6c4128c..1d0b236f2e7a 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -260,7 +260,7 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -285,7 +285,7 @@ cpu1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -310,7 +310,7 @@ cpu2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -335,7 +335,7 @@ cpu3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -360,7 +360,7 @@ cpu4: cpu@4 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <4>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -385,7 +385,7 @@ cpu5: cpu@5 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <5>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -410,7 +410,7 @@ cpu6: cpu@6 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <6>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -435,7 +435,7 @@ cpu7: cpu@7 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <7>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -460,7 +460,7 @@ cpu8: cpu@8 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <8>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -485,7 +485,7 @@ cpu9: cpu@9 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <9>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -510,7 +510,7 @@ cpu10: cpu@10 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <10>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -535,7 +535,7 @@ cpu11: cpu@11 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <11>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -560,7 +560,7 @@ cpu12: cpu@12 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <12>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -585,7 +585,7 @@ cpu13: cpu@13 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <13>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -610,7 +610,7 @@ cpu14: cpu@14 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <14>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -635,7 +635,7 @@ cpu15: cpu@15 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <15>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -660,7 +660,7 @@ cpu16: cpu@16 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <16>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -685,7 +685,7 @@ cpu17: cpu@17 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <17>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -710,7 +710,7 @@ cpu18: cpu@18 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <18>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -735,7 +735,7 @@ cpu19: cpu@19 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <19>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -760,7 +760,7 @@ cpu20: cpu@20 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <20>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -785,7 +785,7 @@ cpu21: cpu@21 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <21>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -810,7 +810,7 @@ cpu22: cpu@22 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <22>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -835,7 +835,7 @@ cpu23: cpu@23 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <23>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -860,7 +860,7 @@ cpu24: cpu@24 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <24>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -885,7 +885,7 @@ cpu25: cpu@25 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <25>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -910,7 +910,7 @@ cpu26: cpu@26 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <26>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -935,7 +935,7 @@ cpu27: cpu@27 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <27>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -960,7 +960,7 @@ cpu28: cpu@28 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <28>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -985,7 +985,7 @@ cpu29: cpu@29 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <29>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1010,7 +1010,7 @@ cpu30: cpu@30 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <30>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1035,7 +1035,7 @@ cpu31: cpu@31 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <31>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1060,7 +1060,7 @@ cpu32: cpu@32 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <32>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1085,7 +1085,7 @@ cpu33: cpu@33 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <33>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1110,7 +1110,7 @@ cpu34: cpu@34 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <34>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1135,7 +1135,7 @@ cpu35: cpu@35 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <35>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1160,7 +1160,7 @@ cpu36: cpu@36 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <36>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1185,7 +1185,7 @@ cpu37: cpu@37 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <37>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1210,7 +1210,7 @@ cpu38: cpu@38 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <38>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1235,7 +1235,7 @@ cpu39: cpu@39 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <39>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1260,7 +1260,7 @@ cpu40: cpu@40 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <40>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1285,7 +1285,7 @@ cpu41: cpu@41 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <41>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1310,7 +1310,7 @@ cpu42: cpu@42 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <42>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1335,7 +1335,7 @@ cpu43: cpu@43 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <43>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1360,7 +1360,7 @@ cpu44: cpu@44 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <44>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1385,7 +1385,7 @@ cpu45: cpu@45 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <45>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1410,7 +1410,7 @@ cpu46: cpu@46 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <46>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1435,7 +1435,7 @@ cpu47: cpu@47 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <47>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1460,7 +1460,7 @@ cpu48: cpu@48 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <48>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1485,7 +1485,7 @@ cpu49: cpu@49 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <49>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1510,7 +1510,7 @@ cpu50: cpu@50 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <50>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1535,7 +1535,7 @@ cpu51: cpu@51 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <51>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1560,7 +1560,7 @@ cpu52: cpu@52 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <52>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1585,7 +1585,7 @@ cpu53: cpu@53 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <53>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1610,7 +1610,7 @@ cpu54: cpu@54 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <54>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1635,7 +1635,7 @@ cpu55: cpu@55 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <55>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1660,7 +1660,7 @@ cpu56: cpu@56 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <56>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1685,7 +1685,7 @@ cpu57: cpu@57 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <57>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1710,7 +1710,7 @@ cpu58: cpu@58 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <58>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1735,7 +1735,7 @@ cpu59: cpu@59 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <59>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1760,7 +1760,7 @@ cpu60: cpu@60 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <60>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1785,7 +1785,7 @@ cpu61: cpu@61 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <61>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1810,7 +1810,7 @@ cpu62: cpu@62 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <62>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1835,7 +1835,7 @@ cpu63: cpu@63 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadpmu";
 			reg = <63>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
-- 
2.34.1


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[PATCH v7 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520

[Yu Chien Peter Lin]

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v4 -> v5:
  - New patch
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ba4d2c673ac8..2dad2b22824a 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -22,7 +22,7 @@ c910_0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -46,7 +46,7 @@ c910_1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -70,7 +70,7 @@ c910_2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -94,7 +94,7 @@ c910_3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
-- 
2.34.1


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[PATCH v7 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f

[Yu Chien Peter Lin]

xandespmu stands for Andes Performance Monitor Unit extension.
Based on the added Andes PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - No change
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Geert's Reviewed-by
  - Include Prabhakar's Reviewed/Tested-by
Changes v5 -> v6:
  - Include Conor's Acked-by
Changes v6 -> v7:
  - No change
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 099f3df75b42..d7a66043f13b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -27,7 +27,7 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xandespmu";
 			mmu-type = "riscv,sv39";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <0x40>;
-- 
2.34.1


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[PATCH v7 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events

[Yu Chien Peter Lin]

From: Locus Wei-Han Chen <locus84@andestech.com>

Add the Andes AX45 JSON files that allows specifying symbolic event
names for the raw PMU events.

Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v1 -> v2:
  - No change
Changes v2 -> v3:
  - No change
Changes v3 -> v4:
  - No change
Changes v4 -> v5:
  - Include Prabhakar's Tested-by
Changes v5 -> v6:
  - No change
Changes v6 -> v7:
  - No change
---
 .../arch/riscv/andes/ax45/firmware.json       |  68 ++++++++++
 .../arch/riscv/andes/ax45/instructions.json   | 127 ++++++++++++++++++
 .../arch/riscv/andes/ax45/memory.json         |  57 ++++++++
 .../arch/riscv/andes/ax45/microarch.json      |  77 +++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |   1 +
 5 files changed, 330 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json

diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
@@ -0,0 +1,68 @@
+[
+  {
+    "ArchStdEvent": "FW_MISALIGNED_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_MISALIGNED_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ILLEGAL_INSN"
+  },
+  {
+    "ArchStdEvent": "FW_SET_TIMER"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
new file mode 100644
index 000000000000..713a08c1a40f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
@@ -0,0 +1,127 @@
+[
+	{
+		"EventCode": "0x10",
+		"EventName": "cycle_count",
+		"BriefDescription": "Cycle count"
+	},
+	{
+		"EventCode": "0x20",
+		"EventName": "inst_count",
+		"BriefDescription": "Retired instruction count"
+	},
+	{
+		"EventCode": "0x30",
+		"EventName": "int_load_inst",
+		"BriefDescription": "Integer load instruction count"
+	},
+	{
+		"EventCode": "0x40",
+		"EventName": "int_store_inst",
+		"BriefDescription": "Integer store instruction count"
+	},
+	{
+		"EventCode": "0x50",
+		"EventName": "atomic_inst",
+		"BriefDescription": "Atomic instruction count"
+	},
+	{
+		"EventCode": "0x60",
+		"EventName": "sys_inst",
+		"BriefDescription": "System instruction count"
+	},
+	{
+		"EventCode": "0x70",
+		"EventName": "int_compute_inst",
+		"BriefDescription": "Integer computational instruction count"
+	},
+	{
+		"EventCode": "0x80",
+		"EventName": "condition_br",
+		"BriefDescription": "Conditional branch instruction count"
+	},
+	{
+		"EventCode": "0x90",
+		"EventName": "taken_condition_br",
+		"BriefDescription": "Taken conditional branch instruction count"
+	},
+	{
+		"EventCode": "0xA0",
+		"EventName": "jal_inst",
+		"BriefDescription": "JAL instruction count"
+	},
+	{
+		"EventCode": "0xB0",
+		"EventName": "jalr_inst",
+		"BriefDescription": "JALR instruction count"
+	},
+	{
+		"EventCode": "0xC0",
+		"EventName": "ret_inst",
+		"BriefDescription": "Return instruction count"
+	},
+	{
+		"EventCode": "0xD0",
+		"EventName": "control_trans_inst",
+		"BriefDescription": "Control transfer instruction count"
+	},
+	{
+		"EventCode": "0xE0",
+		"EventName": "ex9_inst",
+		"BriefDescription": "EXEC.IT instruction count"
+	},
+	{
+		"EventCode": "0xF0",
+		"EventName": "int_mul_inst",
+		"BriefDescription": "Integer multiplication instruction count"
+	},
+	{
+		"EventCode": "0x100",
+		"EventName": "int_div_rem_inst",
+		"BriefDescription": "Integer division/remainder instruction count"
+	},
+	{
+		"EventCode": "0x110",
+		"EventName": "float_load_inst",
+		"BriefDescription": "Floating-point load instruction count"
+	},
+	{
+		"EventCode": "0x120",
+		"EventName": "float_store_inst",
+		"BriefDescription": "Floating-point store instruction count"
+	},
+	{
+		"EventCode": "0x130",
+		"EventName": "float_add_sub_inst",
+		"BriefDescription": "Floating-point addition/subtraction instruction count"
+	},
+	{
+		"EventCode": "0x140",
+		"EventName": "float_mul_inst",
+		"BriefDescription": "Floating-point multiplication instruction count"
+	},
+	{
+		"EventCode": "0x150",
+		"EventName": "float_fused_muladd_inst",
+		"BriefDescription": "Floating-point fused multiply-add instruction count"
+	},
+	{
+		"EventCode": "0x160",
+		"EventName": "float_div_sqrt_inst",
+		"BriefDescription": "Floating-point division or square-root instruction count"
+	},
+	{
+		"EventCode": "0x170",
+		"EventName": "other_float_inst",
+		"BriefDescription": "Other floating-point instruction count"
+	},
+	{
+		"EventCode": "0x180",
+		"EventName": "int_mul_add_sub_inst",
+		"BriefDescription": "Integer multiplication and add/sub instruction count"
+	},
+	{
+		"EventCode": "0x190",
+		"EventName": "retired_ops",
+		"BriefDescription": "Retired operation count"
+	}
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
new file mode 100644
index 000000000000..c7401b526c77
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
@@ -0,0 +1,57 @@
+[
+	{
+		"EventCode": "0x01",
+		"EventName": "ilm_access",
+		"BriefDescription": "ILM access"
+	},
+	{
+		"EventCode": "0x11",
+		"EventName": "dlm_access",
+		"BriefDescription": "DLM access"
+	},
+	{
+		"EventCode": "0x21",
+		"EventName": "icache_access",
+		"BriefDescription": "ICACHE access"
+	},
+	{
+		"EventCode": "0x31",
+		"EventName": "icache_miss",
+		"BriefDescription": "ICACHE miss"
+	},
+	{
+		"EventCode": "0x41",
+		"EventName": "dcache_access",
+		"BriefDescription": "DCACHE access"
+	},
+	{
+		"EventCode": "0x51",
+		"EventName": "dcache_miss",
+		"BriefDescription": "DCACHE miss"
+	},
+	{
+		"EventCode": "0x61",
+		"EventName": "dcache_load_access",
+		"BriefDescription": "DCACHE load access"
+	},
+	{
+		"EventCode": "0x71",
+		"EventName": "dcache_load_miss",
+		"BriefDescription": "DCACHE load miss"
+	},
+	{
+		"EventCode": "0x81",
+		"EventName": "dcache_store_access",
+		"BriefDescription": "DCACHE store access"
+	},
+	{
+		"EventCode": "0x91",
+		"EventName": "dcache_store_miss",
+		"BriefDescription": "DCACHE store miss"
+	},
+	{
+		"EventCode": "0xA1",
+		"EventName": "dcache_wb",
+		"BriefDescription": "DCACHE writeback"
+	}
+]
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
new file mode 100644
index 000000000000..a6d378cbaa74
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
@@ -0,0 +1,77 @@
+[
+	{
+		"EventCode": "0xB1",
+		"EventName": "cycle_wait_icache_fill",
+		"BriefDescription": "Cycles waiting for ICACHE fill data"
+	},
+	{
+		"EventCode": "0xC1",
+		"EventName": "cycle_wait_dcache_fill",
+		"BriefDescription": "Cycles waiting for DCACHE fill data"
+	},
+	{
+		"EventCode": "0xD1",
+		"EventName": "uncached_ifetch_from_bus",
+		"BriefDescription": "Uncached ifetch data access from bus"
+	},
+	{
+		"EventCode": "0xE1",
+		"EventName": "uncached_load_from_bus",
+		"BriefDescription": "Uncached load data access from bus"
+	},
+	{
+		"EventCode": "0xF1",
+		"EventName": "cycle_wait_uncached_ifetch",
+		"BriefDescription": "Cycles waiting for uncached ifetch data from bus"
+	},
+	{
+		"EventCode": "0x101",
+		"EventName": "cycle_wait_uncached_load",
+		"BriefDescription": "Cycles waiting for uncached load data from bus"
+	},
+	{
+		"EventCode": "0x111",
+		"EventName": "main_itlb_access",
+		"BriefDescription": "Main ITLB access"
+	},
+	{
+		"EventCode": "0x121",
+		"EventName": "main_itlb_miss",
+		"BriefDescription": "Main ITLB miss"
+	},
+	{
+		"EventCode": "0x131",
+		"EventName": "main_dtlb_access",
+		"BriefDescription": "Main DTLB access"
+	},
+	{
+		"EventCode": "0x141",
+		"EventName": "main_dtlb_miss",
+		"BriefDescription": "Main DTLB miss"
+	},
+	{
+		"EventCode": "0x151",
+		"EventName": "cycle_wait_itlb_fill",
+		"BriefDescription": "Cycles waiting for Main ITLB fill data"
+	},
+	{
+		"EventCode": "0x161",
+		"EventName": "pipe_stall_cycle_dtlb_miss",
+		"BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
+	},
+	{
+		"EventCode": "0x02",
+		"EventName": "mispredict_condition_br",
+		"BriefDescription": "Misprediction of conditional branches"
+	},
+	{
+		"EventCode": "0x12",
+		"EventName": "mispredict_take_condition_br",
+		"BriefDescription": "Misprediction of taken conditional branches"
+	},
+	{
+		"EventCode": "0x22",
+		"EventName": "mispredict_target_ret_inst",
+		"BriefDescription": "Misprediction of targets of Return instructions"
+	}
+]
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index c61b3d6ef616..5bf09af14c1b 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -15,3 +15,4 @@
 #
 #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
-- 
2.34.1


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Re: [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number

[Anup Patel]

On Wed, Jan 10, 2024 at 1:10 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Currently, the implementation of the RISC-V INTC driver uses the
> interrupt cause as the hardware interrupt number, with a maximum of
> 64 interrupts. However, the platform can expand the interrupt number
> further for custom local interrupts.
>
> To fully utilize the available local interrupt sources, switch
> to using irq_domain_create_tree() that creates the radix tree
> map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
> and riscv_intc_custom_nr_irqs) to determine the valid range of local
> interrupt number (hwirq).
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
> Changes v1 -> v2:
>   - Fixed irq mapping failure checking (suggested by Clément and Anup)
> Changes v2 -> v3:
>   - No change
> Changes v3 -> v4: (Suggested by Thomas [1])
>   - Use pr_warn_ratelimited instead
>   - Fix coding style and commit message
> Changes v4 -> v5: (Suggested by Thomas)
>   - Fix commit message
> Changes v5 -> v6: (Suggested by Anup [2])
>   - Add riscv_intc_* global variables for checking range in riscv_intc_domain_alloc()
>   - Advertise the number of interrupts allowed
> Changes v6 -> v7:
>   - No functional change
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
> [2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
> ---
>  drivers/irqchip/irq-riscv-intc.c | 30 +++++++++++++++++++++++-------
>  1 file changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index e8d01b14ccdd..b13a16b164c9 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -19,15 +19,17 @@
>  #include <linux/smp.h>
>
>  static struct irq_domain *intc_domain;
> +static unsigned int riscv_intc_nr_irqs __ro_after_init;
> +static unsigned int riscv_intc_custom_base __ro_after_init;
> +static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
>
>  static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
>  {
>         unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
>
> -       if (unlikely(cause >= BITS_PER_LONG))
> -               panic("unexpected interrupt cause");
> -
> -       generic_handle_domain_irq(intc_domain, cause);
> +       if (generic_handle_domain_irq(intc_domain, cause))
> +               pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
> +                                   cause);
>  }
>
>  /*
> @@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
>         if (ret)
>                 return ret;
>
> +       /*
> +        * Only allow hwirq for which we have corresponding standard or
> +        * custom interrupt enable register.
> +        */
> +       if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
> +           (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
> +               return -EINVAL;
> +
>         for (i = 0; i < nr_irqs; i++) {
>                 ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
>                 if (ret)
> @@ -117,8 +127,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
>  {
>         int rc;
>
> -       intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
> -                                              &riscv_intc_domain_ops, NULL);
> +       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
>         if (!intc_domain) {
>                 pr_err("unable to add IRQ domain\n");
>                 return -ENXIO;
> @@ -132,7 +141,10 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
>
>         riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
>
> -       pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> +       pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
> +       if (riscv_intc_custom_nr_irqs)
> +               pr_info("%d custom local interrupts mapped\n",
> +                       riscv_intc_custom_nr_irqs);
>
>         return 0;
>  }
> @@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node,
>                 return 0;
>         }
>
> +       riscv_intc_nr_irqs = BITS_PER_LONG;
> +       riscv_intc_custom_base = riscv_intc_nr_irqs;
> +       riscv_intc_custom_nr_irqs = 0;
> +
>         return riscv_intc_init_common(of_node_to_fwnode(node));
>  }
>
> --
> 2.34.1
>

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Re: [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

[Anup Patel]

On Wed, Jan 10, 2024 at 1:10 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
>   cpu0: cpu@0 {
>       compatible = "andestech,ax45mp", "riscv";
>       ...
>       cpu0-intc: interrupt-controller {
>           #interrupt-cells = <0x01>;
>           compatible = "andestech,cpu-intc", "riscv,cpu-intc";
>           interrupt-controller;
>       };
>   };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - Return -ENXIO if no valid compatible INTC found
>   - Allow falling back to generic RISC-V INTC
> Changes v3 -> v4: (Suggested by Thomas [1])
>   - Add comment to andes irq chip function
>   - Refine code flow to share with generic RISC-V INTC and ACPI
>   - Move Andes specific definitions to include/linux/soc/andes/irq.h
> Changes v4 -> v5: (Suggested by Thomas)
>   - Fix commit message
>   - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
>   - Do not set chip_data to the chip itself with irq_domain_set_info()
>   - Follow reverse fir tree order variable declarations
> Changes v5 -> v6:
>   - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI
>   - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup)
>   - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32)
> Changes v6 -> v7:
>   - No change
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> ---
>  drivers/irqchip/irq-riscv-intc.c | 66 +++++++++++++++++++++++++++-----
>  include/linux/soc/andes/irq.h    | 18 +++++++++
>  2 files changed, 74 insertions(+), 10 deletions(-)
>  create mode 100644 include/linux/soc/andes/irq.h
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index b13a16b164c9..7064857f1f1d 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -17,6 +17,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/smp.h>
> +#include <linux/soc/andes/irq.h>
>
>  static struct irq_domain *intc_domain;
>  static unsigned int riscv_intc_nr_irqs __ro_after_init;
> @@ -49,6 +50,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
>         csr_set(CSR_IE, BIT(d->hwirq));
>  }
>
> +static void andes_intc_irq_mask(struct irq_data *d)
> +{
> +       /*
> +        * Andes specific S-mode local interrupt causes (hwirq)
> +        * are defined as (256 + n) and controlled by n-th bit
> +        * of SLIE.
> +        */
> +       unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> +
> +       if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> +               csr_clear(CSR_IE, mask);
> +       else
> +               csr_clear(ANDES_CSR_SLIE, mask);
> +}
> +
> +static void andes_intc_irq_unmask(struct irq_data *d)
> +{
> +       unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> +
> +       if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> +               csr_set(CSR_IE, mask);
> +       else
> +               csr_set(ANDES_CSR_SLIE, mask);
> +}
> +
>  static void riscv_intc_irq_eoi(struct irq_data *d)
>  {
>         /*
> @@ -72,12 +98,21 @@ static struct irq_chip riscv_intc_chip = {
>         .irq_eoi = riscv_intc_irq_eoi,
>  };
>
> +static struct irq_chip andes_intc_chip = {
> +       .name           = "RISC-V INTC",
> +       .irq_mask       = andes_intc_irq_mask,
> +       .irq_unmask     = andes_intc_irq_unmask,
> +       .irq_eoi        = riscv_intc_irq_eoi,
> +};
> +
>  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
>                                  irq_hw_number_t hwirq)
>  {
> +       struct irq_chip *chip = d->host_data;
> +
>         irq_set_percpu_devid(irq);
> -       irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> -                           handle_percpu_devid_irq, NULL, NULL);
> +       irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
> +                           NULL, NULL);
>
>         return 0;
>  }
> @@ -123,11 +158,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
>         return intc_domain->fwnode;
>  }
>
> -static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> +static int __init riscv_intc_init_common(struct fwnode_handle *fn,
> +                                        struct irq_chip *chip)
>  {
>         int rc;
>
> -       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> +       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
>         if (!intc_domain) {
>                 pr_err("unable to add IRQ domain\n");
>                 return -ENXIO;
> @@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
>  static int __init riscv_intc_init(struct device_node *node,
>                                   struct device_node *parent)
>  {
> -       int rc;
> +       struct irq_chip *chip;
>         unsigned long hartid;
> +       int rc;
>
>         rc = riscv_of_parent_hartid(node, &hartid);
>         if (rc < 0) {
> @@ -178,14 +215,23 @@ static int __init riscv_intc_init(struct device_node *node,
>                 return 0;
>         }
>
> -       riscv_intc_nr_irqs = BITS_PER_LONG;
> -       riscv_intc_custom_base = riscv_intc_nr_irqs;
> -       riscv_intc_custom_nr_irqs = 0;
> +       if (of_device_is_compatible(node, "andestech,cpu-intc")) {
> +               riscv_intc_nr_irqs = BITS_PER_LONG;
> +               riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
> +               riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
> +               chip = &andes_intc_chip;
> +       } else {
> +               riscv_intc_nr_irqs = BITS_PER_LONG;
> +               riscv_intc_custom_base = riscv_intc_nr_irqs;
> +               riscv_intc_custom_nr_irqs = 0;
> +               chip = &riscv_intc_chip;
> +       }
>
> -       return riscv_intc_init_common(of_node_to_fwnode(node));
> +       return riscv_intc_init_common(of_node_to_fwnode(node), chip);
>  }
>
>  IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
> +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
>
>  #ifdef CONFIG_ACPI
>
> @@ -212,7 +258,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
>                 return -ENOMEM;
>         }
>
> -       return riscv_intc_init_common(fn);
> +       return riscv_intc_init_common(fn, &riscv_intc_chip);
>  }
>
>  IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
> diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
> new file mode 100644
> index 000000000000..edc3182d6e66
> --- /dev/null
> +++ b/include/linux/soc/andes/irq.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2023 Andes Technology Corporation
> + */
> +#ifndef __ANDES_IRQ_H
> +#define __ANDES_IRQ_H
> +
> +/* Andes PMU irq number */
> +#define ANDES_RV_IRQ_PMOVI             18
> +#define ANDES_RV_IRQ_LAST              ANDES_RV_IRQ_PMOVI
> +#define ANDES_SLI_CAUSE_BASE           256
> +
> +/* Andes PMU related registers */
> +#define ANDES_CSR_SLIE                 0x9c4
> +#define ANDES_CSR_SLIP                 0x9c5
> +#define ANDES_CSR_SCOUNTEROF           0x9d4
> +
> +#endif /* __ANDES_IRQ_H */
> --
> 2.34.1
>

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Re: [PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations

[Atish Patra]

On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> The interrupt enable/disable operations are already performed by the
> IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
> enable_percpu_irq()/disable_percpu_irq(). It can be done only once.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
> in the initial PATCH3 [1].
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/
>
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - No change
> Changes v3 -> v4:
>   - No change
> Changes v4 -> v5:
>   - No change
> Changes v5 -> v6:
>   - No change
> Changes v6 -> v7:
>   - No change
> ---
>  drivers/perf/riscv_pmu_sbi.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 16acd4dcdb96..2edbc37abadf 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
>         if (riscv_pmu_use_irq) {
>                 cpu_hw_evt->irq = riscv_pmu_irq;
>                 csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
> -               csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
>                 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
>         }
>
> @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
>  {
>         if (riscv_pmu_use_irq) {
>                 disable_percpu_irq(riscv_pmu_irq);
> -               csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
>         }
>
>         /* Disable all counters access for user mode now */
> --
> 2.34.1
>

Reviewed-by: Atish Patra <atishp@rivosinc.com>

-- 
Regards,
Atish

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Re: [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

[Atish Patra]

On Wed, Jan 10, 2024 at 7:13 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Jan 10, 2024 at 1:10 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add support for the Andes hart-level interrupt controller. This
> > controller provides interrupt mask/unmask functions to access the
> > custom register (SLIE) where the non-standard S-mode local interrupt
> > enable bits are located. The base of custom interrupt number is set
> > to 256.
> >
> > To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> > ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> > passed to the irq_domain_set_info() as a private data.
> >
> > Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> > compatible string to be present in interrupt-controller of cpu node to
> > enable the use of custom local interrupt source.
> > e.g.,
> >
> >   cpu0: cpu@0 {
> >       compatible = "andestech,ax45mp", "riscv";
> >       ...
> >       cpu0-intc: interrupt-controller {
> >           #interrupt-cells = <0x01>;
> >           compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> >           interrupt-controller;
> >       };
> >   };
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Randolph <randolph@andestech.com>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> Regards,
> Anup
>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > Changes v2 -> v3:
> >   - Return -ENXIO if no valid compatible INTC found
> >   - Allow falling back to generic RISC-V INTC
> > Changes v3 -> v4: (Suggested by Thomas [1])
> >   - Add comment to andes irq chip function
> >   - Refine code flow to share with generic RISC-V INTC and ACPI
> >   - Move Andes specific definitions to include/linux/soc/andes/irq.h
> > Changes v4 -> v5: (Suggested by Thomas)
> >   - Fix commit message
> >   - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
> >   - Do not set chip_data to the chip itself with irq_domain_set_info()
> >   - Follow reverse fir tree order variable declarations
> > Changes v5 -> v6:
> >   - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI
> >   - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup)
> >   - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32)
> > Changes v6 -> v7:
> >   - No change
> >
> > [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/
> > ---
> >  drivers/irqchip/irq-riscv-intc.c | 66 +++++++++++++++++++++++++++-----
> >  include/linux/soc/andes/irq.h    | 18 +++++++++
> >  2 files changed, 74 insertions(+), 10 deletions(-)
> >  create mode 100644 include/linux/soc/andes/irq.h
> >
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index b13a16b164c9..7064857f1f1d 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -17,6 +17,7 @@
> >  #include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/smp.h>
> > +#include <linux/soc/andes/irq.h>
> >
> >  static struct irq_domain *intc_domain;
> >  static unsigned int riscv_intc_nr_irqs __ro_after_init;
> > @@ -49,6 +50,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
> >         csr_set(CSR_IE, BIT(d->hwirq));
> >  }
> >
> > +static void andes_intc_irq_mask(struct irq_data *d)
> > +{
> > +       /*
> > +        * Andes specific S-mode local interrupt causes (hwirq)
> > +        * are defined as (256 + n) and controlled by n-th bit
> > +        * of SLIE.
> > +        */
> > +       unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> > +
> > +       if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > +               csr_clear(CSR_IE, mask);
> > +       else
> > +               csr_clear(ANDES_CSR_SLIE, mask);
> > +}
> > +
> > +static void andes_intc_irq_unmask(struct irq_data *d)
> > +{
> > +       unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> > +
> > +       if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > +               csr_set(CSR_IE, mask);
> > +       else
> > +               csr_set(ANDES_CSR_SLIE, mask);
> > +}
> > +
> >  static void riscv_intc_irq_eoi(struct irq_data *d)
> >  {
> >         /*
> > @@ -72,12 +98,21 @@ static struct irq_chip riscv_intc_chip = {
> >         .irq_eoi = riscv_intc_irq_eoi,
> >  };
> >
> > +static struct irq_chip andes_intc_chip = {
> > +       .name           = "RISC-V INTC",
> > +       .irq_mask       = andes_intc_irq_mask,
> > +       .irq_unmask     = andes_intc_irq_unmask,
> > +       .irq_eoi        = riscv_intc_irq_eoi,
> > +};
> > +
> >  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
> >                                  irq_hw_number_t hwirq)
> >  {
> > +       struct irq_chip *chip = d->host_data;
> > +
> >         irq_set_percpu_devid(irq);
> > -       irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> > -                           handle_percpu_devid_irq, NULL, NULL);
> > +       irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
> > +                           NULL, NULL);
> >
> >         return 0;
> >  }
> > @@ -123,11 +158,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
> >         return intc_domain->fwnode;
> >  }
> >
> > -static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> > +static int __init riscv_intc_init_common(struct fwnode_handle *fn,
> > +                                        struct irq_chip *chip)
> >  {
> >         int rc;
> >
> > -       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> > +       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
> >         if (!intc_domain) {
> >                 pr_err("unable to add IRQ domain\n");
> >                 return -ENXIO;
> > @@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> >  static int __init riscv_intc_init(struct device_node *node,
> >                                   struct device_node *parent)
> >  {
> > -       int rc;
> > +       struct irq_chip *chip;
> >         unsigned long hartid;
> > +       int rc;
> >
> >         rc = riscv_of_parent_hartid(node, &hartid);
> >         if (rc < 0) {
> > @@ -178,14 +215,23 @@ static int __init riscv_intc_init(struct device_node *node,
> >                 return 0;
> >         }
> >
> > -       riscv_intc_nr_irqs = BITS_PER_LONG;
> > -       riscv_intc_custom_base = riscv_intc_nr_irqs;
> > -       riscv_intc_custom_nr_irqs = 0;
> > +       if (of_device_is_compatible(node, "andestech,cpu-intc")) {
> > +               riscv_intc_nr_irqs = BITS_PER_LONG;
> > +               riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
> > +               riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
> > +               chip = &andes_intc_chip;

There may be similar usage of custom interrupt space in the future as
well. I think it will be better if we define a generic structure and
vendor
specific registration mechanism based on compatible strings. This will
avoid a bunch of if else blocks here.

> > +       } else {
> > +               riscv_intc_nr_irqs = BITS_PER_LONG;
> > +               riscv_intc_custom_base = riscv_intc_nr_irqs;
> > +               riscv_intc_custom_nr_irqs = 0;
> > +               chip = &riscv_intc_chip;
> > +       }
> >
> > -       return riscv_intc_init_common(of_node_to_fwnode(node));
> > +       return riscv_intc_init_common(of_node_to_fwnode(node), chip);
> >  }
> >
> >  IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
> > +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
> >
> >  #ifdef CONFIG_ACPI
> >
> > @@ -212,7 +258,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
> >                 return -ENOMEM;
> >         }
> >
> > -       return riscv_intc_init_common(fn);
> > +       return riscv_intc_init_common(fn, &riscv_intc_chip);
> >  }
> >
> >  IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
> > diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
> > new file mode 100644
> > index 000000000000..edc3182d6e66
> > --- /dev/null
> > +++ b/include/linux/soc/andes/irq.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 Andes Technology Corporation
> > + */
> > +#ifndef __ANDES_IRQ_H
> > +#define __ANDES_IRQ_H
> > +
> > +/* Andes PMU irq number */
> > +#define ANDES_RV_IRQ_PMOVI             18
> > +#define ANDES_RV_IRQ_LAST              ANDES_RV_IRQ_PMOVI
> > +#define ANDES_SLI_CAUSE_BASE           256
> > +
> > +/* Andes PMU related registers */
> > +#define ANDES_CSR_SLIE                 0x9c4
> > +#define ANDES_CSR_SLIP                 0x9c5
> > +#define ANDES_CSR_SCOUNTEROF           0x9d4
> > +
> > +#endif /* __ANDES_IRQ_H */
> > --
> > 2.34.1
> >



-- 
Regards,
Atish

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Re: [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number

[Atish Patra]

On Wed, Jan 10, 2024 at 7:11 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Jan 10, 2024 at 1:10 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as the hardware interrupt number, with a maximum of
> > 64 interrupts. However, the platform can expand the interrupt number
> > further for custom local interrupts.
> >
> > To fully utilize the available local interrupt sources, switch
> > to using irq_domain_create_tree() that creates the radix tree
> > map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
> > and riscv_intc_custom_nr_irqs) to determine the valid range of local
> > interrupt number (hwirq).
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Randolph <randolph@andestech.com>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> Regards,
> Anup
>
> > ---
> > Changes v1 -> v2:
> >   - Fixed irq mapping failure checking (suggested by Clément and Anup)
> > Changes v2 -> v3:
> >   - No change
> > Changes v3 -> v4: (Suggested by Thomas [1])
> >   - Use pr_warn_ratelimited instead
> >   - Fix coding style and commit message
> > Changes v4 -> v5: (Suggested by Thomas)
> >   - Fix commit message
> > Changes v5 -> v6: (Suggested by Anup [2])
> >   - Add riscv_intc_* global variables for checking range in riscv_intc_domain_alloc()
> >   - Advertise the number of interrupts allowed
> > Changes v6 -> v7:
> >   - No functional change
> >
> > [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085
> > [2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
> > ---
> >  drivers/irqchip/irq-riscv-intc.c | 30 +++++++++++++++++++++++-------
> >  1 file changed, 23 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> > index e8d01b14ccdd..b13a16b164c9 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -19,15 +19,17 @@
> >  #include <linux/smp.h>
> >
> >  static struct irq_domain *intc_domain;
> > +static unsigned int riscv_intc_nr_irqs __ro_after_init;
> > +static unsigned int riscv_intc_custom_base __ro_after_init;
> > +static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
> >
> >  static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
> >  {
> >         unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
> >
> > -       if (unlikely(cause >= BITS_PER_LONG))
> > -               panic("unexpected interrupt cause");
> > -
> > -       generic_handle_domain_irq(intc_domain, cause);
> > +       if (generic_handle_domain_irq(intc_domain, cause))
> > +               pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
> > +                                   cause);
> >  }
> >
> >  /*
> > @@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
> >         if (ret)
> >                 return ret;
> >
> > +       /*
> > +        * Only allow hwirq for which we have corresponding standard or
> > +        * custom interrupt enable register.
> > +        */
> > +       if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
> > +           (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
> > +               return -EINVAL;
> > +
> >         for (i = 0; i < nr_irqs; i++) {
> >                 ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
> >                 if (ret)
> > @@ -117,8 +127,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> >  {
> >         int rc;
> >
> > -       intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
> > -                                              &riscv_intc_domain_ops, NULL);
> > +       intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
> >         if (!intc_domain) {
> >                 pr_err("unable to add IRQ domain\n");
> >                 return -ENXIO;
> > @@ -132,7 +141,10 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> >
> >         riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
> >
> > -       pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> > +       pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
> > +       if (riscv_intc_custom_nr_irqs)
> > +               pr_info("%d custom local interrupts mapped\n",
> > +                       riscv_intc_custom_nr_irqs);
> >
> >         return 0;
> >  }
> > @@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node,
> >                 return 0;
> >         }
> >
> > +       riscv_intc_nr_irqs = BITS_PER_LONG;
> > +       riscv_intc_custom_base = riscv_intc_nr_irqs;
> > +       riscv_intc_custom_nr_irqs = 0;
> > +
> >         return riscv_intc_init_common(of_node_to_fwnode(node));
> >  }
> >
> > --
> > 2.34.1
> >


Reviewed-by: Atish Patra <atishp@rivosinc.com>

-- 
Regards,
Atish

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Re: [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string

[Atish Patra]

On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add "andestech,cpu-intc" compatible string to indicate that
> Andes specific local interrupt is supported on the core,
> e.g. AX45MP cores have 3 types of non-standard local interrupt
> which can be handled in supervisor mode:
>

PATCH1 in this series renames everything from ANDESTECH to ANDES to be
consistent.
Here you are adding DT binding with "andestech". Is there any
fundamental difference between these two to demand
this change ?

FYI: I don't mind either way as I don't have skin in the game. Just
something I noticed while reviewing the series.

> - Slave port ECC error interrupt
> - Bus write transaction error interrupt
> - Performance monitor overflow interrupt
>
> These interrupts are enabled/disabled via a custom register
> SLIE instead of the standard interrupt enable register SIE.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - Updated commit message
>   - Fixed possible compatibles for Andes INTC
> Changes v3 -> v4:
>   - Add const entry instead of enum (Suggested by Conor)
> Changes v4 -> v5:
>   - Include Conor's Acked-by
>   - Include Prabhakar's Reviewed-by
> Changes v5 -> v6:
>   - No change
> Changes v6 -> v7:
>   - No change
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 23646b684ea2..33c2b620a59f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -101,7 +101,11 @@ properties:
>          const: 1
>
>        compatible:
> -        const: riscv,cpu-intc
> +        oneOf:
> +          - items:
> +              - const: andestech,cpu-intc
> +              - const: riscv,cpu-intc
> +          - const: riscv,cpu-intc
>
>        interrupt-controller: true
>
> --
> 2.34.1
>


-- 
Regards,
Atish

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Re: [PATCH v7 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events

[Atish Patra]

On Tue, Jan 9, 2024 at 11:41 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> From: Locus Wei-Han Chen <locus84@andestech.com>
>
> Add the Andes AX45 JSON files that allows specifying symbolic event
> names for the raw PMU events.
>
> Signed-off-by: Locus Wei-Han Chen <locus84@andestech.com>
> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Changes v1 -> v2:
>   - No change
> Changes v2 -> v3:
>   - No change
> Changes v3 -> v4:
>   - No change
> Changes v4 -> v5:
>   - Include Prabhakar's Tested-by
> Changes v5 -> v6:
>   - No change
> Changes v6 -> v7:
>   - No change
> ---
>  .../arch/riscv/andes/ax45/firmware.json       |  68 ++++++++++
>  .../arch/riscv/andes/ax45/instructions.json   | 127 ++++++++++++++++++
>  .../arch/riscv/andes/ax45/memory.json         |  57 ++++++++
>  .../arch/riscv/andes/ax45/microarch.json      |  77 +++++++++++
>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |   1 +
>  5 files changed, 330 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
> new file mode 100644
> index 000000000000..9b4a032186a7
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
> @@ -0,0 +1,68 @@
> +[
> +  {
> +    "ArchStdEvent": "FW_MISALIGNED_LOAD"
> +  },
> +  {
> +    "ArchStdEvent": "FW_MISALIGNED_STORE"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ACCESS_LOAD"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ACCESS_STORE"
> +  },
> +  {
> +    "ArchStdEvent": "FW_ILLEGAL_INSN"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SET_TIMER"
> +  },
> +  {
> +    "ArchStdEvent": "FW_IPI_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_IPI_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_FENCE_I_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> +  },
> +  {
> +    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> +  }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
> new file mode 100644
> index 000000000000..713a08c1a40f
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
> @@ -0,0 +1,127 @@
> +[
> +       {
> +               "EventCode": "0x10",
> +               "EventName": "cycle_count",
> +               "BriefDescription": "Cycle count"
> +       },
> +       {
> +               "EventCode": "0x20",
> +               "EventName": "inst_count",
> +               "BriefDescription": "Retired instruction count"
> +       },
> +       {
> +               "EventCode": "0x30",
> +               "EventName": "int_load_inst",
> +               "BriefDescription": "Integer load instruction count"
> +       },
> +       {
> +               "EventCode": "0x40",
> +               "EventName": "int_store_inst",
> +               "BriefDescription": "Integer store instruction count"
> +       },
> +       {
> +               "EventCode": "0x50",
> +               "EventName": "atomic_inst",
> +               "BriefDescription": "Atomic instruction count"
> +       },
> +       {
> +               "EventCode": "0x60",
> +               "EventName": "sys_inst",
> +               "BriefDescription": "System instruction count"
> +       },
> +       {
> +               "EventCode": "0x70",
> +               "EventName": "int_compute_inst",
> +               "BriefDescription": "Integer computational instruction count"
> +       },
> +       {
> +               "EventCode": "0x80",
> +               "EventName": "condition_br",
> +               "BriefDescription": "Conditional branch instruction count"
> +       },
> +       {
> +               "EventCode": "0x90",
> +               "EventName": "taken_condition_br",
> +               "BriefDescription": "Taken conditional branch instruction count"
> +       },
> +       {
> +               "EventCode": "0xA0",
> +               "EventName": "jal_inst",
> +               "BriefDescription": "JAL instruction count"
> +       },
> +       {
> +               "EventCode": "0xB0",
> +               "EventName": "jalr_inst",
> +               "BriefDescription": "JALR instruction count"
> +       },
> +       {
> +               "EventCode": "0xC0",
> +               "EventName": "ret_inst",
> +               "BriefDescription": "Return instruction count"
> +       },
> +       {
> +               "EventCode": "0xD0",
> +               "EventName": "control_trans_inst",
> +               "BriefDescription": "Control transfer instruction count"
> +       },
> +       {
> +               "EventCode": "0xE0",
> +               "EventName": "ex9_inst",
> +               "BriefDescription": "EXEC.IT instruction count"
> +       },
> +       {
> +               "EventCode": "0xF0",
> +               "EventName": "int_mul_inst",
> +               "BriefDescription": "Integer multiplication instruction count"
> +       },
> +       {
> +               "EventCode": "0x100",
> +               "EventName": "int_div_rem_inst",
> +               "BriefDescription": "Integer division/remainder instruction count"
> +       },
> +       {
> +               "EventCode": "0x110",
> +               "EventName": "float_load_inst",
> +               "BriefDescription": "Floating-point load instruction count"
> +       },
> +       {
> +               "EventCode": "0x120",
> +               "EventName": "float_store_inst",
> +               "BriefDescription": "Floating-point store instruction count"
> +       },
> +       {
> +               "EventCode": "0x130",
> +               "EventName": "float_add_sub_inst",
> +               "BriefDescription": "Floating-point addition/subtraction instruction count"
> +       },
> +       {
> +               "EventCode": "0x140",
> +               "EventName": "float_mul_inst",
> +               "BriefDescription": "Floating-point multiplication instruction count"
> +       },
> +       {
> +               "EventCode": "0x150",
> +               "EventName": "float_fused_muladd_inst",
> +               "BriefDescription": "Floating-point fused multiply-add instruction count"
> +       },
> +       {
> +               "EventCode": "0x160",
> +               "EventName": "float_div_sqrt_inst",
> +               "BriefDescription": "Floating-point division or square-root instruction count"
> +       },
> +       {
> +               "EventCode": "0x170",
> +               "EventName": "other_float_inst",
> +               "BriefDescription": "Other floating-point instruction count"
> +       },
> +       {
> +               "EventCode": "0x180",
> +               "EventName": "int_mul_add_sub_inst",
> +               "BriefDescription": "Integer multiplication and add/sub instruction count"
> +       },
> +       {
> +               "EventCode": "0x190",
> +               "EventName": "retired_ops",
> +               "BriefDescription": "Retired operation count"
> +       }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
> new file mode 100644
> index 000000000000..c7401b526c77
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
> @@ -0,0 +1,57 @@
> +[
> +       {
> +               "EventCode": "0x01",
> +               "EventName": "ilm_access",
> +               "BriefDescription": "ILM access"
> +       },
> +       {
> +               "EventCode": "0x11",
> +               "EventName": "dlm_access",
> +               "BriefDescription": "DLM access"
> +       },
> +       {
> +               "EventCode": "0x21",
> +               "EventName": "icache_access",
> +               "BriefDescription": "ICACHE access"
> +       },
> +       {
> +               "EventCode": "0x31",
> +               "EventName": "icache_miss",
> +               "BriefDescription": "ICACHE miss"
> +       },
> +       {
> +               "EventCode": "0x41",
> +               "EventName": "dcache_access",
> +               "BriefDescription": "DCACHE access"
> +       },
> +       {
> +               "EventCode": "0x51",
> +               "EventName": "dcache_miss",
> +               "BriefDescription": "DCACHE miss"
> +       },
> +       {
> +               "EventCode": "0x61",
> +               "EventName": "dcache_load_access",
> +               "BriefDescription": "DCACHE load access"
> +       },
> +       {
> +               "EventCode": "0x71",
> +               "EventName": "dcache_load_miss",
> +               "BriefDescription": "DCACHE load miss"
> +       },
> +       {
> +               "EventCode": "0x81",
> +               "EventName": "dcache_store_access",
> +               "BriefDescription": "DCACHE store access"
> +       },
> +       {
> +               "EventCode": "0x91",
> +               "EventName": "dcache_store_miss",
> +               "BriefDescription": "DCACHE store miss"
> +       },
> +       {
> +               "EventCode": "0xA1",
> +               "EventName": "dcache_wb",
> +               "BriefDescription": "DCACHE writeback"
> +       }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
> new file mode 100644
> index 000000000000..a6d378cbaa74
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
> @@ -0,0 +1,77 @@
> +[
> +       {
> +               "EventCode": "0xB1",
> +               "EventName": "cycle_wait_icache_fill",
> +               "BriefDescription": "Cycles waiting for ICACHE fill data"
> +       },
> +       {
> +               "EventCode": "0xC1",
> +               "EventName": "cycle_wait_dcache_fill",
> +               "BriefDescription": "Cycles waiting for DCACHE fill data"
> +       },
> +       {
> +               "EventCode": "0xD1",
> +               "EventName": "uncached_ifetch_from_bus",
> +               "BriefDescription": "Uncached ifetch data access from bus"
> +       },
> +       {
> +               "EventCode": "0xE1",
> +               "EventName": "uncached_load_from_bus",
> +               "BriefDescription": "Uncached load data access from bus"
> +       },
> +       {
> +               "EventCode": "0xF1",
> +               "EventName": "cycle_wait_uncached_ifetch",
> +               "BriefDescription": "Cycles waiting for uncached ifetch data from bus"
> +       },
> +       {
> +               "EventCode": "0x101",
> +               "EventName": "cycle_wait_uncached_load",
> +               "BriefDescription": "Cycles waiting for uncached load data from bus"
> +       },
> +       {
> +               "EventCode": "0x111",
> +               "EventName": "main_itlb_access",
> +               "BriefDescription": "Main ITLB access"
> +       },
> +       {
> +               "EventCode": "0x121",
> +               "EventName": "main_itlb_miss",
> +               "BriefDescription": "Main ITLB miss"
> +       },
> +       {
> +               "EventCode": "0x131",
> +               "EventName": "main_dtlb_access",
> +               "BriefDescription": "Main DTLB access"
> +       },
> +       {
> +               "EventCode": "0x141",
> +               "EventName": "main_dtlb_miss",
> +               "BriefDescription": "Main DTLB miss"
> +       },
> +       {
> +               "EventCode": "0x151",
> +               "EventName": "cycle_wait_itlb_fill",
> +               "BriefDescription": "Cycles waiting for Main ITLB fill data"
> +       },
> +       {
> +               "EventCode": "0x161",
> +               "EventName": "pipe_stall_cycle_dtlb_miss",
> +               "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
> +       },
> +       {
> +               "EventCode": "0x02",
> +               "EventName": "mispredict_condition_br",
> +               "BriefDescription": "Misprediction of conditional branches"
> +       },
> +       {
> +               "EventCode": "0x12",
> +               "EventName": "mispredict_take_condition_br",
> +               "BriefDescription": "Misprediction of taken conditional branches"
> +       },
> +       {
> +               "EventCode": "0x22",
> +               "EventName": "mispredict_target_ret_inst",
> +               "BriefDescription": "Misprediction of targets of Return instructions"
> +       }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> index c61b3d6ef616..5bf09af14c1b 100644
> --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -15,3 +15,4 @@
>  #
>  #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
>  0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> +0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core
> --
> 2.34.1
>

Acked-by: Atish Patra <atishp@rivosinc.com>

-- 
Regards,
Atish

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Re: [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2675 bytes --]

On Fri, Jan 12, 2024 at 03:50:15PM -0800, Atish Patra wrote:
> On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add "andestech,cpu-intc" compatible string to indicate that
> > Andes specific local interrupt is supported on the core,
> > e.g. AX45MP cores have 3 types of non-standard local interrupt
> > which can be handled in supervisor mode:
> >
> 
> PATCH1 in this series renames everything from ANDESTECH to ANDES to be
> consistent.
> Here you are adding DT binding with "andestech". Is there any
> fundamental difference between these two to demand
> this change ?

This one is the vendor prefix and the company has been assigned
"andestech" and they're not getting a second one. The rename of the
variables is a bit gratuitous tbf.

Cheers,
Conor.

> FYI: I don't mind either way as I don't have skin in the game. Just
> something I noticed while reviewing the series.
> 
> > - Slave port ECC error interrupt
> > - Bus write transaction error interrupt
> > - Performance monitor overflow interrupt
> >
> > These interrupts are enabled/disabled via a custom register
> > SLIE instead of the standard interrupt enable register SIE.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > Changes v2 -> v3:
> >   - Updated commit message
> >   - Fixed possible compatibles for Andes INTC
> > Changes v3 -> v4:
> >   - Add const entry instead of enum (Suggested by Conor)
> > Changes v4 -> v5:
> >   - Include Conor's Acked-by
> >   - Include Prabhakar's Reviewed-by
> > Changes v5 -> v6:
> >   - No change
> > Changes v6 -> v7:
> >   - No change
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 23646b684ea2..33c2b620a59f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -101,7 +101,11 @@ properties:
> >          const: 1
> >
> >        compatible:
> > -        const: riscv,cpu-intc
> > +        oneOf:
> > +          - items:
> > +              - const: andestech,cpu-intc
> > +              - const: riscv,cpu-intc
> > +          - const: riscv,cpu-intc
> >
> >        interrupt-controller: true
> >
> > --
> > 2.34.1
> >
> 
> 
> -- 
> Regards,
> Atish

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Re: [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string

[Atish Patra]

On Fri, Jan 12, 2024 at 4:19 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Jan 12, 2024 at 03:50:15PM -0800, Atish Patra wrote:
> > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > <peterlin@andestech.com> wrote:
> > >
> > > Add "andestech,cpu-intc" compatible string to indicate that
> > > Andes specific local interrupt is supported on the core,
> > > e.g. AX45MP cores have 3 types of non-standard local interrupt
> > > which can be handled in supervisor mode:
> > >
> >
> > PATCH1 in this series renames everything from ANDESTECH to ANDES to be
> > consistent.
> > Here you are adding DT binding with "andestech". Is there any
> > fundamental difference between these two to demand
> > this change ?
>
> This one is the vendor prefix and the company has been assigned
> "andestech" and they're not getting a second one. The rename of the

Thanks for the clarification.

> variables is a bit gratuitous tbf.
>

I felt the same.

> Cheers,
> Conor.
>
> > FYI: I don't mind either way as I don't have skin in the game. Just
> > something I noticed while reviewing the series.
> >
> > > - Slave port ECC error interrupt
> > > - Bus write transaction error interrupt
> > > - Performance monitor overflow interrupt
> > >
> > > These interrupts are enabled/disabled via a custom register
> > > SLIE instead of the standard interrupt enable register SIE.
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > Changes v1 -> v2:
> > >   - New patch
> > > Changes v2 -> v3:
> > >   - Updated commit message
> > >   - Fixed possible compatibles for Andes INTC
> > > Changes v3 -> v4:
> > >   - Add const entry instead of enum (Suggested by Conor)
> > > Changes v4 -> v5:
> > >   - Include Conor's Acked-by
> > >   - Include Prabhakar's Reviewed-by
> > > Changes v5 -> v6:
> > >   - No change
> > > Changes v6 -> v7:
> > >   - No change
> > > ---
> > >  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index 23646b684ea2..33c2b620a59f 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -101,7 +101,11 @@ properties:
> > >          const: 1
> > >
> > >        compatible:
> > > -        const: riscv,cpu-intc
> > > +        oneOf:
> > > +          - items:
> > > +              - const: andestech,cpu-intc
> > > +              - const: riscv,cpu-intc
> > > +          - const: riscv,cpu-intc
> > >
> > >        interrupt-controller: true
> > >
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > Regards,
> > Atish



-- 
Regards,
Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Atish Patra]

On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> The custom PMU extension aims to support perf event sampling prior
> to the ratification of Sscofpmf. Instead of diverting the bits and
> register reserved for future standard, a set of custom registers is
> added.  Hence, we may consider it as a CPU feature rather than an
> erratum.
>

I don't think we should do that. Any custom implementation that
violates the standard RISC-V spec should
be an errata not a feature.
As per my understanding, a vendor can call an extension custom ISA
extension if the same feature is not available
in the standard ISA extensions or the mechanism is completely
different. It must also not violate any standard spec as well.

In this case, a standard sscofpmf is already available. Moreover, both
Andes and T-head extensions violate the standard
spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
are clearly specified as reserved for standard local interrupts
in the AIA specification.

Please implementation Andes PMU support as an errata as well similar to T-head


> T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> for proper functioning as of this commit.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Changes v1 -> v2:
>   - New patch
> Changes v2 -> v3:
>   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> Changes v3 -> v4:
>   - No change
> Changes v4 -> v5:
>   - Include Guo's Reviewed-by
>   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> Changes v5 -> v6:
>   - Include Conor's Reviewed-by
> Changes v6 -> v7:
>   - No change
> ---
>  arch/riscv/Kconfig.errata            | 13 -------------
>  arch/riscv/errata/thead/errata.c     | 19 -------------------
>  arch/riscv/include/asm/errata_list.h | 15 +--------------
>  arch/riscv/include/asm/hwcap.h       |  1 +
>  arch/riscv/kernel/cpufeature.c       |  1 +
>  drivers/perf/Kconfig                 | 13 +++++++++++++
>  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
>  7 files changed, 30 insertions(+), 51 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e2c731cfed8c..0d19f47d1018 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
>
>           If you don't know what to do here, say "Y".
>
> -config ERRATA_THEAD_PMU
> -       bool "Apply T-Head PMU errata"
> -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> -       default y
> -       help
> -         The T-Head C9xx cores implement a PMU overflow extension very
> -         similar to the core SSCOFPMF extension.
> -
> -         This will apply the overflow errata to handle the non-standard
> -         behaviour via the regular SBI PMU driver and interface.
> -
> -         If you don't know what to do here, say "Y".
> -
>  endmenu # "CPU errata selection"
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 0554ed4bf087..5de5f7209132 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
>         return true;
>  }
>
> -static bool errata_probe_pmu(unsigned int stage,
> -                            unsigned long arch_id, unsigned long impid)
> -{
> -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> -               return false;
> -
> -       /* target-c9xx cores report arch_id and impid as 0 */
> -       if (arch_id != 0 || impid != 0)
> -               return false;
> -
> -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> -               return false;
> -
> -       return true;
> -}
> -
>  static u32 thead_errata_probe(unsigned int stage,
>                               unsigned long archid, unsigned long impid)
>  {
> @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
>         if (errata_probe_cmo(stage, archid, impid))
>                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>
> -       if (errata_probe_pmu(stage, archid, impid))
> -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> -
>         return cpu_req_errata;
>  }
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 4ed21a62158c..9bccc2ba0eb5 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -25,8 +25,7 @@
>  #ifdef CONFIG_ERRATA_THEAD
>  #define        ERRATA_THEAD_PBMT 0
>  #define        ERRATA_THEAD_CMO 1
> -#define        ERRATA_THEAD_PMU 2
> -#define        ERRATA_THEAD_NUMBER 3
> +#define        ERRATA_THEAD_NUMBER 2
>  #endif
>
>  #ifdef __ASSEMBLY__
> @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
>             "r"((unsigned long)(_start) + (_size))                      \
>         : "a0")
>
> -#define THEAD_C9XX_RV_IRQ_PMU                  17
> -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> -
> -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> -asm volatile(ALTERNATIVE(                                              \
> -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> -               CONFIG_ERRATA_THEAD_PMU)                                \
> -       : "=r" (__ovl) :                                                \
> -       : "memory")
> -
>  #endif /* __ASSEMBLY__ */
>
>  #endif
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..480f9da7fba7 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,7 @@
>  #define RISCV_ISA_EXT_ZFA              71
>  #define RISCV_ISA_EXT_ZTSO             72
>  #define RISCV_ISA_EXT_ZACAS            73
> +#define RISCV_ISA_EXT_XTHEADPMU                74
>
>  #define RISCV_ISA_EXT_MAX              128
>  #define RISCV_ISA_EXT_INVALID          U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index e32591e9da90..4aded5bf8fc3 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
>         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
>         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
>  };
>
>  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> index 273d67ecf6d2..6cef15ec7c25 100644
> --- a/drivers/perf/Kconfig
> +++ b/drivers/perf/Kconfig
> @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
>           full perf feature support i.e. counter overflow, privilege mode
>           filtering, counter configuration.
>
> +config THEAD_CUSTOM_PMU
> +       bool "T-Head custom PMU support"
> +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> +       default y
> +       help
> +         The T-Head C9xx cores implement a PMU overflow extension very
> +         similar to the core SSCOFPMF extension.
> +
> +         This will patch the overflow CSR and handle the non-standard
> +         behaviour via the regular SBI PMU driver and interface.
> +
> +         If you don't know what to do here, say "Y".
> +
>  config ARM_PMU_ACPI
>         depends on ARM_PMU && ACPI
>         def_bool y
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 2edbc37abadf..31ca79846399 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -20,10 +20,21 @@
>  #include <linux/cpu_pm.h>
>  #include <linux/sched/clock.h>
>
> -#include <asm/errata_list.h>
>  #include <asm/sbi.h>
>  #include <asm/cpufeature.h>
>
> +#define THEAD_C9XX_RV_IRQ_PMU          17
> +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> +
> +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> +asm volatile(ALTERNATIVE(                                              \
> +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> +               CONFIG_THEAD_CUSTOM_PMU)                                \
> +       : "=r" (__ovl) :                                                \
> +       : "memory")
> +
>  #define SYSCTL_NO_USER_ACCESS  0
>  #define SYSCTL_USER_ACCESS     1
>  #define SYSCTL_LEGACY          2
> @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
>         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
>                 riscv_pmu_irq_num = RV_IRQ_PMU;
>                 riscv_pmu_use_irq = true;
> -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> -                  riscv_cached_marchid(0) == 0 &&
> -                  riscv_cached_mimpid(0) == 0) {
> +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
>                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
>                 riscv_pmu_use_irq = true;
>         }
> --
> 2.34.1
>


--
Regards,
Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 12470 bytes --]

On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > The custom PMU extension aims to support perf event sampling prior
> > to the ratification of Sscofpmf. Instead of diverting the bits and
> > register reserved for future standard, a set of custom registers is
> > added.  Hence, we may consider it as a CPU feature rather than an
> > erratum.
> >
> 
> I don't think we should do that. Any custom implementation that
> violates the standard RISC-V spec should
> be an errata not a feature.
> As per my understanding, a vendor can call an extension custom ISA
> extension if the same feature is not available
> in the standard ISA extensions or the mechanism is completely
> different. It must also not violate any standard spec as well.
> 
> In this case, a standard sscofpmf is already available. Moreover, both
> Andes and T-head extensions violate the standard
> spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> are clearly specified as reserved for standard local interrupts
> in the AIA specification.

I disagree with you here. The Andes implementation predated (IIRC that
is what was said in replies to an earlier revision) the Sscofpmf
extension and certainly predates the AIA specification. I would be on
board with this line of thinking if someone comes along in 2030 with
"Zbb but with this one tweak" or where something flies entirely in the
face of the standard (like the IOCP cache stuff). The relevant section
in the AIA spec seems to say:
| Interrupt causes that are standardized by the Privileged Architecture
| have major identities in the range 0–15, while numbers 16 and higher are
| officially available for platform standards or for custom use.
| The Advanced Interrupt Architecture claims further authority over
| identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
| range 24–31 and all major identities 48 and higher still free for custom
| use.
I don't see how that can be problematic given the Andes implemtation
dates from before AIA was a thing. It would be silly to say that because
an optional extension later came along and took over something previously
allowed for indiscriminate custom use, that support for that custom
extension is not permitted.

I may well be missing something here though, you clearly know these
specs better than I do, but from what I have read I disagree.

> Please implementation Andes PMU support as an errata as well similar to T-head

I certainly _do not_ want to see things like this detected via lookup
tables of marchid and co in the kernel unless it is absolutely required.
We have standard probing mechanisms for feature detection (because to me
this _is_ a feature) and they should be used. Additionally, we define what
entries in the DT properties mean, and if it is convenient to put
"psuedo" extensions into the DT, then we should do so. Getting away from
being tied to what RVI decrees was one of the goals of the new
properties after all, so that we could use a standard mechanism of DT
probing for things like this.

Thanks,
Conor.

> > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > for proper functioning as of this commit.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Guo Ren <guoren@kernel.org>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > Changes v2 -> v3:
> >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > Changes v3 -> v4:
> >   - No change
> > Changes v4 -> v5:
> >   - Include Guo's Reviewed-by
> >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > Changes v5 -> v6:
> >   - Include Conor's Reviewed-by
> > Changes v6 -> v7:
> >   - No change
> > ---
> >  arch/riscv/Kconfig.errata            | 13 -------------
> >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> >  arch/riscv/include/asm/hwcap.h       |  1 +
> >  arch/riscv/kernel/cpufeature.c       |  1 +
> >  drivers/perf/Kconfig                 | 13 +++++++++++++
> >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> >  7 files changed, 30 insertions(+), 51 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index e2c731cfed8c..0d19f47d1018 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> >
> >           If you don't know what to do here, say "Y".
> >
> > -config ERRATA_THEAD_PMU
> > -       bool "Apply T-Head PMU errata"
> > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > -       default y
> > -       help
> > -         The T-Head C9xx cores implement a PMU overflow extension very
> > -         similar to the core SSCOFPMF extension.
> > -
> > -         This will apply the overflow errata to handle the non-standard
> > -         behaviour via the regular SBI PMU driver and interface.
> > -
> > -         If you don't know what to do here, say "Y".
> > -
> >  endmenu # "CPU errata selection"
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index 0554ed4bf087..5de5f7209132 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> >         return true;
> >  }
> >
> > -static bool errata_probe_pmu(unsigned int stage,
> > -                            unsigned long arch_id, unsigned long impid)
> > -{
> > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > -               return false;
> > -
> > -       /* target-c9xx cores report arch_id and impid as 0 */
> > -       if (arch_id != 0 || impid != 0)
> > -               return false;
> > -
> > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > -               return false;
> > -
> > -       return true;
> > -}
> > -
> >  static u32 thead_errata_probe(unsigned int stage,
> >                               unsigned long archid, unsigned long impid)
> >  {
> > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> >         if (errata_probe_cmo(stage, archid, impid))
> >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> >
> > -       if (errata_probe_pmu(stage, archid, impid))
> > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > -
> >         return cpu_req_errata;
> >  }
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 4ed21a62158c..9bccc2ba0eb5 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -25,8 +25,7 @@
> >  #ifdef CONFIG_ERRATA_THEAD
> >  #define        ERRATA_THEAD_PBMT 0
> >  #define        ERRATA_THEAD_CMO 1
> > -#define        ERRATA_THEAD_PMU 2
> > -#define        ERRATA_THEAD_NUMBER 3
> > +#define        ERRATA_THEAD_NUMBER 2
> >  #endif
> >
> >  #ifdef __ASSEMBLY__
> > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> >             "r"((unsigned long)(_start) + (_size))                      \
> >         : "a0")
> >
> > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > -
> > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > -asm volatile(ALTERNATIVE(                                              \
> > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > -       : "=r" (__ovl) :                                                \
> > -       : "memory")
> > -
> >  #endif /* __ASSEMBLY__ */
> >
> >  #endif
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..480f9da7fba7 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,7 @@
> >  #define RISCV_ISA_EXT_ZFA              71
> >  #define RISCV_ISA_EXT_ZTSO             72
> >  #define RISCV_ISA_EXT_ZACAS            73
> > +#define RISCV_ISA_EXT_XTHEADPMU                74
> >
> >  #define RISCV_ISA_EXT_MAX              128
> >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index e32591e9da90..4aded5bf8fc3 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> >  };
> >
> >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > index 273d67ecf6d2..6cef15ec7c25 100644
> > --- a/drivers/perf/Kconfig
> > +++ b/drivers/perf/Kconfig
> > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> >           full perf feature support i.e. counter overflow, privilege mode
> >           filtering, counter configuration.
> >
> > +config THEAD_CUSTOM_PMU
> > +       bool "T-Head custom PMU support"
> > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > +       default y
> > +       help
> > +         The T-Head C9xx cores implement a PMU overflow extension very
> > +         similar to the core SSCOFPMF extension.
> > +
> > +         This will patch the overflow CSR and handle the non-standard
> > +         behaviour via the regular SBI PMU driver and interface.
> > +
> > +         If you don't know what to do here, say "Y".
> > +
> >  config ARM_PMU_ACPI
> >         depends on ARM_PMU && ACPI
> >         def_bool y
> > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > index 2edbc37abadf..31ca79846399 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -20,10 +20,21 @@
> >  #include <linux/cpu_pm.h>
> >  #include <linux/sched/clock.h>
> >
> > -#include <asm/errata_list.h>
> >  #include <asm/sbi.h>
> >  #include <asm/cpufeature.h>
> >
> > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > +
> > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > +asm volatile(ALTERNATIVE(                                              \
> > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > +       : "=r" (__ovl) :                                                \
> > +       : "memory")
> > +
> >  #define SYSCTL_NO_USER_ACCESS  0
> >  #define SYSCTL_USER_ACCESS     1
> >  #define SYSCTL_LEGACY          2
> > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> >                 riscv_pmu_use_irq = true;
> > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > -                  riscv_cached_marchid(0) == 0 &&
> > -                  riscv_cached_mimpid(0) == 0) {
> > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> >                 riscv_pmu_use_irq = true;
> >         }
> > --
> > 2.34.1
> >
> 
> 
> --
> Regards,
> Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Anup Patel]

On Wed, Jan 17, 2024 at 2:26 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > The custom PMU extension aims to support perf event sampling prior
> > to the ratification of Sscofpmf. Instead of diverting the bits and
> > register reserved for future standard, a set of custom registers is
> > added.  Hence, we may consider it as a CPU feature rather than an
> > erratum.
> >
>
> I don't think we should do that. Any custom implementation that
> violates the standard RISC-V spec should
> be an errata not a feature.
> As per my understanding, a vendor can call an extension custom ISA
> extension if the same feature is not available
> in the standard ISA extensions or the mechanism is completely
> different. It must also not violate any standard spec as well.

I agree with Atish here. There is a well defined encoding space for
custom extensions.

If a custom extension spills over to standard encoding space then
it should be treated as an errata and not a proper custom extension.

>
> In this case, a standard sscofpmf is already available. Moreover, both
> Andes and T-head extensions violate the standard
> spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> are clearly specified as reserved for standard local interrupts
> in the AIA specification.
>
> Please implementation Andes PMU support as an errata as well similar to T-head
>
>
> > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > for proper functioning as of this commit.

T-Head has many violations of using standard encoding space. I don't see
why this series should be touching T-Head erratas.

If Andes custom PMU CSRs are defined in custom encoding space then
Andes PMU can be treated as proper custom extension.

Regards,
Anup

> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Guo Ren <guoren@kernel.org>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > Changes v2 -> v3:
> >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > Changes v3 -> v4:
> >   - No change
> > Changes v4 -> v5:
> >   - Include Guo's Reviewed-by
> >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > Changes v5 -> v6:
> >   - Include Conor's Reviewed-by
> > Changes v6 -> v7:
> >   - No change
> > ---
> >  arch/riscv/Kconfig.errata            | 13 -------------
> >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> >  arch/riscv/include/asm/hwcap.h       |  1 +
> >  arch/riscv/kernel/cpufeature.c       |  1 +
> >  drivers/perf/Kconfig                 | 13 +++++++++++++
> >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> >  7 files changed, 30 insertions(+), 51 deletions(-)
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index e2c731cfed8c..0d19f47d1018 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> >
> >           If you don't know what to do here, say "Y".
> >
> > -config ERRATA_THEAD_PMU
> > -       bool "Apply T-Head PMU errata"
> > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > -       default y
> > -       help
> > -         The T-Head C9xx cores implement a PMU overflow extension very
> > -         similar to the core SSCOFPMF extension.
> > -
> > -         This will apply the overflow errata to handle the non-standard
> > -         behaviour via the regular SBI PMU driver and interface.
> > -
> > -         If you don't know what to do here, say "Y".
> > -
> >  endmenu # "CPU errata selection"
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index 0554ed4bf087..5de5f7209132 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> >         return true;
> >  }
> >
> > -static bool errata_probe_pmu(unsigned int stage,
> > -                            unsigned long arch_id, unsigned long impid)
> > -{
> > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > -               return false;
> > -
> > -       /* target-c9xx cores report arch_id and impid as 0 */
> > -       if (arch_id != 0 || impid != 0)
> > -               return false;
> > -
> > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > -               return false;
> > -
> > -       return true;
> > -}
> > -
> >  static u32 thead_errata_probe(unsigned int stage,
> >                               unsigned long archid, unsigned long impid)
> >  {
> > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> >         if (errata_probe_cmo(stage, archid, impid))
> >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> >
> > -       if (errata_probe_pmu(stage, archid, impid))
> > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > -
> >         return cpu_req_errata;
> >  }
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 4ed21a62158c..9bccc2ba0eb5 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -25,8 +25,7 @@
> >  #ifdef CONFIG_ERRATA_THEAD
> >  #define        ERRATA_THEAD_PBMT 0
> >  #define        ERRATA_THEAD_CMO 1
> > -#define        ERRATA_THEAD_PMU 2
> > -#define        ERRATA_THEAD_NUMBER 3
> > +#define        ERRATA_THEAD_NUMBER 2
> >  #endif
> >
> >  #ifdef __ASSEMBLY__
> > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> >             "r"((unsigned long)(_start) + (_size))                      \
> >         : "a0")
> >
> > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > -
> > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > -asm volatile(ALTERNATIVE(                                              \
> > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > -       : "=r" (__ovl) :                                                \
> > -       : "memory")
> > -
> >  #endif /* __ASSEMBLY__ */
> >
> >  #endif
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..480f9da7fba7 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,7 @@
> >  #define RISCV_ISA_EXT_ZFA              71
> >  #define RISCV_ISA_EXT_ZTSO             72
> >  #define RISCV_ISA_EXT_ZACAS            73
> > +#define RISCV_ISA_EXT_XTHEADPMU                74
> >
> >  #define RISCV_ISA_EXT_MAX              128
> >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index e32591e9da90..4aded5bf8fc3 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> >  };
> >
> >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > index 273d67ecf6d2..6cef15ec7c25 100644
> > --- a/drivers/perf/Kconfig
> > +++ b/drivers/perf/Kconfig
> > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> >           full perf feature support i.e. counter overflow, privilege mode
> >           filtering, counter configuration.
> >
> > +config THEAD_CUSTOM_PMU
> > +       bool "T-Head custom PMU support"
> > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > +       default y
> > +       help
> > +         The T-Head C9xx cores implement a PMU overflow extension very
> > +         similar to the core SSCOFPMF extension.
> > +
> > +         This will patch the overflow CSR and handle the non-standard
> > +         behaviour via the regular SBI PMU driver and interface.
> > +
> > +         If you don't know what to do here, say "Y".
> > +
> >  config ARM_PMU_ACPI
> >         depends on ARM_PMU && ACPI
> >         def_bool y
> > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > index 2edbc37abadf..31ca79846399 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -20,10 +20,21 @@
> >  #include <linux/cpu_pm.h>
> >  #include <linux/sched/clock.h>
> >
> > -#include <asm/errata_list.h>
> >  #include <asm/sbi.h>
> >  #include <asm/cpufeature.h>
> >
> > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > +
> > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > +asm volatile(ALTERNATIVE(                                              \
> > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > +       : "=r" (__ovl) :                                                \
> > +       : "memory")
> > +
> >  #define SYSCTL_NO_USER_ACCESS  0
> >  #define SYSCTL_USER_ACCESS     1
> >  #define SYSCTL_LEGACY          2
> > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> >                 riscv_pmu_use_irq = true;
> > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > -                  riscv_cached_marchid(0) == 0 &&
> > -                  riscv_cached_mimpid(0) == 0) {
> > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> >                 riscv_pmu_use_irq = true;
> >         }
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish
>
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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Atish Patra]

On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > <peterlin@andestech.com> wrote:
> > >
> > > The custom PMU extension aims to support perf event sampling prior
> > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > register reserved for future standard, a set of custom registers is
> > > added.  Hence, we may consider it as a CPU feature rather than an
> > > erratum.
> > >
> >
> > I don't think we should do that. Any custom implementation that
> > violates the standard RISC-V spec should
> > be an errata not a feature.
> > As per my understanding, a vendor can call an extension custom ISA
> > extension if the same feature is not available
> > in the standard ISA extensions or the mechanism is completely
> > different. It must also not violate any standard spec as well.
> >
> > In this case, a standard sscofpmf is already available. Moreover, both
> > Andes and T-head extensions violate the standard
> > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > are clearly specified as reserved for standard local interrupts
> > in the AIA specification.
>
> I disagree with you here. The Andes implementation predated (IIRC that
> is what was said in replies to an earlier revision) the Sscofpmf
> extension and certainly predates the AIA specification. I would be on
> board with this line of thinking if someone comes along in 2030 with
> "Zbb but with this one tweak" or where something flies entirely in the
> face of the standard (like the IOCP cache stuff). The relevant section
> in the AIA spec seems to say:
> | Interrupt causes that are standardized by the Privileged Architecture
> | have major identities in the range 0–15, while numbers 16 and higher are
> | officially available for platform standards or for custom use.
> | The Advanced Interrupt Architecture claims further authority over
> | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
> | range 24–31 and all major identities 48 and higher still free for custom
> | use.
> I don't see how that can be problematic given the Andes implemtation
> dates from before AIA was a thing. It would be silly to say that because
> an optional extension later came along and took over something previously
> allowed for indiscriminate custom use, that support for that custom
> extension is not permitted.
>

AIA is not some optional extension. It defines the RISC-V interrupt
architecture going forward and will be the default implementation
in the future. IMO, this will be a slippery slope if we start
supporting custom implementations to override interrupt ID definitions
via custom cpu features. T-head implementation works perfectly fine as
an errata and I don't understand why
there is a push to make it a cpu feature. We should try to improve the
ecosystem for future platforms rather than bending
backwards to support older implementations.

I understand the push to brand this as a custom extension if current
errata/alternative can't support it. But I don't think that's the case
here though. Please correct me if I am wrong.

> I may well be missing something here though, you clearly know these
> specs better than I do, but from what I have read I disagree.
>
> > Please implementation Andes PMU support as an errata as well similar to T-head
>
> I certainly _do not_ want to see things like this detected via lookup
> tables of marchid and co in the kernel unless it is absolutely required.
> We have standard probing mechanisms for feature detection (because to me
> this _is_ a feature) and they should be used. Additionally, we define what
> entries in the DT properties mean, and if it is convenient to put
> "psuedo" extensions into the DT, then we should do so. Getting away from
> being tied to what RVI decrees was one of the goals of the new
> properties after all, so that we could use a standard mechanism of DT
> probing for things like this.
>

Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
I'm sure we'll have many of those, which will be leveraged via pseudo
extensions in the DT.
However, these shouldn't co-exist with standard ISA extensions in the
namespace in riscv_isa_ext and/or hwprobe.
The vendor-specific extensions should be defined under a
vendor-specific namespace.
This was another issue with this series as well. I didn't raise this
topic earlier because I don't think overriding interrupt
identities qualifies for a custom ISA extension

> Thanks,
> Conor.
>
> > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > > for proper functioning as of this commit.
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > Reviewed-by: Guo Ren <guoren@kernel.org>
> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > ---
> > > Changes v1 -> v2:
> > >   - New patch
> > > Changes v2 -> v3:
> > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > > Changes v3 -> v4:
> > >   - No change
> > > Changes v4 -> v5:
> > >   - Include Guo's Reviewed-by
> > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > > Changes v5 -> v6:
> > >   - Include Conor's Reviewed-by
> > > Changes v6 -> v7:
> > >   - No change
> > > ---
> > >  arch/riscv/Kconfig.errata            | 13 -------------
> > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> > >  arch/riscv/include/asm/hwcap.h       |  1 +
> > >  arch/riscv/kernel/cpufeature.c       |  1 +
> > >  drivers/perf/Kconfig                 | 13 +++++++++++++
> > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> > >  7 files changed, 30 insertions(+), 51 deletions(-)
> > >
> > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > index e2c731cfed8c..0d19f47d1018 100644
> > > --- a/arch/riscv/Kconfig.errata
> > > +++ b/arch/riscv/Kconfig.errata
> > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> > >
> > >           If you don't know what to do here, say "Y".
> > >
> > > -config ERRATA_THEAD_PMU
> > > -       bool "Apply T-Head PMU errata"
> > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > > -       default y
> > > -       help
> > > -         The T-Head C9xx cores implement a PMU overflow extension very
> > > -         similar to the core SSCOFPMF extension.
> > > -
> > > -         This will apply the overflow errata to handle the non-standard
> > > -         behaviour via the regular SBI PMU driver and interface.
> > > -
> > > -         If you don't know what to do here, say "Y".
> > > -
> > >  endmenu # "CPU errata selection"
> > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > index 0554ed4bf087..5de5f7209132 100644
> > > --- a/arch/riscv/errata/thead/errata.c
> > > +++ b/arch/riscv/errata/thead/errata.c
> > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> > >         return true;
> > >  }
> > >
> > > -static bool errata_probe_pmu(unsigned int stage,
> > > -                            unsigned long arch_id, unsigned long impid)
> > > -{
> > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > > -               return false;
> > > -
> > > -       /* target-c9xx cores report arch_id and impid as 0 */
> > > -       if (arch_id != 0 || impid != 0)
> > > -               return false;
> > > -
> > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > -               return false;
> > > -
> > > -       return true;
> > > -}
> > > -
> > >  static u32 thead_errata_probe(unsigned int stage,
> > >                               unsigned long archid, unsigned long impid)
> > >  {
> > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> > >         if (errata_probe_cmo(stage, archid, impid))
> > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> > >
> > > -       if (errata_probe_pmu(stage, archid, impid))
> > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > > -
> > >         return cpu_req_errata;
> > >  }
> > >
> > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > > index 4ed21a62158c..9bccc2ba0eb5 100644
> > > --- a/arch/riscv/include/asm/errata_list.h
> > > +++ b/arch/riscv/include/asm/errata_list.h
> > > @@ -25,8 +25,7 @@
> > >  #ifdef CONFIG_ERRATA_THEAD
> > >  #define        ERRATA_THEAD_PBMT 0
> > >  #define        ERRATA_THEAD_CMO 1
> > > -#define        ERRATA_THEAD_PMU 2
> > > -#define        ERRATA_THEAD_NUMBER 3
> > > +#define        ERRATA_THEAD_NUMBER 2
> > >  #endif
> > >
> > >  #ifdef __ASSEMBLY__
> > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> > >             "r"((unsigned long)(_start) + (_size))                      \
> > >         : "a0")
> > >
> > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > > -
> > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > -asm volatile(ALTERNATIVE(                                              \
> > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > > -       : "=r" (__ovl) :                                                \
> > > -       : "memory")
> > > -
> > >  #endif /* __ASSEMBLY__ */
> > >
> > >  #endif
> > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > index 5340f818746b..480f9da7fba7 100644
> > > --- a/arch/riscv/include/asm/hwcap.h
> > > +++ b/arch/riscv/include/asm/hwcap.h
> > > @@ -80,6 +80,7 @@
> > >  #define RISCV_ISA_EXT_ZFA              71
> > >  #define RISCV_ISA_EXT_ZTSO             72
> > >  #define RISCV_ISA_EXT_ZACAS            73
> > > +#define RISCV_ISA_EXT_XTHEADPMU                74
> > >
> > >  #define RISCV_ISA_EXT_MAX              128
> > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index e32591e9da90..4aded5bf8fc3 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> > >  };
> > >
> > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > > index 273d67ecf6d2..6cef15ec7c25 100644
> > > --- a/drivers/perf/Kconfig
> > > +++ b/drivers/perf/Kconfig
> > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> > >           full perf feature support i.e. counter overflow, privilege mode
> > >           filtering, counter configuration.
> > >
> > > +config THEAD_CUSTOM_PMU
> > > +       bool "T-Head custom PMU support"
> > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > > +       default y
> > > +       help
> > > +         The T-Head C9xx cores implement a PMU overflow extension very
> > > +         similar to the core SSCOFPMF extension.
> > > +
> > > +         This will patch the overflow CSR and handle the non-standard
> > > +         behaviour via the regular SBI PMU driver and interface.
> > > +
> > > +         If you don't know what to do here, say "Y".
> > > +
> > >  config ARM_PMU_ACPI
> > >         depends on ARM_PMU && ACPI
> > >         def_bool y
> > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > index 2edbc37abadf..31ca79846399 100644
> > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > @@ -20,10 +20,21 @@
> > >  #include <linux/cpu_pm.h>
> > >  #include <linux/sched/clock.h>
> > >
> > > -#include <asm/errata_list.h>
> > >  #include <asm/sbi.h>
> > >  #include <asm/cpufeature.h>
> > >
> > > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > > +
> > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > +asm volatile(ALTERNATIVE(                                              \
> > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > > +       : "=r" (__ovl) :                                                \
> > > +       : "memory")
> > > +
> > >  #define SYSCTL_NO_USER_ACCESS  0
> > >  #define SYSCTL_USER_ACCESS     1
> > >  #define SYSCTL_LEGACY          2
> > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> > >                 riscv_pmu_use_irq = true;
> > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > > -                  riscv_cached_marchid(0) == 0 &&
> > > -                  riscv_cached_mimpid(0) == 0) {
> > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> > >                 riscv_pmu_use_irq = true;
> > >         }
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > Regards,
> > Atish



-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Atish Patra]

On Tue, Jan 16, 2024 at 7:35 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Wed, Jan 17, 2024 at 2:26 AM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > <peterlin@andestech.com> wrote:
> > >
> > > The custom PMU extension aims to support perf event sampling prior
> > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > register reserved for future standard, a set of custom registers is
> > > added.  Hence, we may consider it as a CPU feature rather than an
> > > erratum.
> > >
> >
> > I don't think we should do that. Any custom implementation that
> > violates the standard RISC-V spec should
> > be an errata not a feature.
> > As per my understanding, a vendor can call an extension custom ISA
> > extension if the same feature is not available
> > in the standard ISA extensions or the mechanism is completely
> > different. It must also not violate any standard spec as well.
>
> I agree with Atish here. There is a well defined encoding space for
> custom extensions.
>
> If a custom extension spills over to standard encoding space then
> it should be treated as an errata and not a proper custom extension.
>
> >
> > In this case, a standard sscofpmf is already available. Moreover, both
> > Andes and T-head extensions violate the standard
> > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > are clearly specified as reserved for standard local interrupts
> > in the AIA specification.
> >
> > Please implementation Andes PMU support as an errata as well similar to T-head
> >
> >
> > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > > for proper functioning as of this commit.
>
> T-Head has many violations of using standard encoding space. I don't see
> why this series should be touching T-Head erratas.
>
> If Andes custom PMU CSRs are defined in custom encoding space then
> Andes PMU can be treated as proper custom extension.
>

The PMU CSRs are in custom extension space.
However, the interrupt ID(18) violates the standard encoding space
defined in AIA.

> Regards,
> Anup
>
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > Reviewed-by: Guo Ren <guoren@kernel.org>
> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > ---
> > > Changes v1 -> v2:
> > >   - New patch
> > > Changes v2 -> v3:
> > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > > Changes v3 -> v4:
> > >   - No change
> > > Changes v4 -> v5:
> > >   - Include Guo's Reviewed-by
> > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > > Changes v5 -> v6:
> > >   - Include Conor's Reviewed-by
> > > Changes v6 -> v7:
> > >   - No change
> > > ---
> > >  arch/riscv/Kconfig.errata            | 13 -------------
> > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> > >  arch/riscv/include/asm/hwcap.h       |  1 +
> > >  arch/riscv/kernel/cpufeature.c       |  1 +
> > >  drivers/perf/Kconfig                 | 13 +++++++++++++
> > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> > >  7 files changed, 30 insertions(+), 51 deletions(-)
> > >
> > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > index e2c731cfed8c..0d19f47d1018 100644
> > > --- a/arch/riscv/Kconfig.errata
> > > +++ b/arch/riscv/Kconfig.errata
> > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> > >
> > >           If you don't know what to do here, say "Y".
> > >
> > > -config ERRATA_THEAD_PMU
> > > -       bool "Apply T-Head PMU errata"
> > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > > -       default y
> > > -       help
> > > -         The T-Head C9xx cores implement a PMU overflow extension very
> > > -         similar to the core SSCOFPMF extension.
> > > -
> > > -         This will apply the overflow errata to handle the non-standard
> > > -         behaviour via the regular SBI PMU driver and interface.
> > > -
> > > -         If you don't know what to do here, say "Y".
> > > -
> > >  endmenu # "CPU errata selection"
> > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > index 0554ed4bf087..5de5f7209132 100644
> > > --- a/arch/riscv/errata/thead/errata.c
> > > +++ b/arch/riscv/errata/thead/errata.c
> > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> > >         return true;
> > >  }
> > >
> > > -static bool errata_probe_pmu(unsigned int stage,
> > > -                            unsigned long arch_id, unsigned long impid)
> > > -{
> > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > > -               return false;
> > > -
> > > -       /* target-c9xx cores report arch_id and impid as 0 */
> > > -       if (arch_id != 0 || impid != 0)
> > > -               return false;
> > > -
> > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > -               return false;
> > > -
> > > -       return true;
> > > -}
> > > -
> > >  static u32 thead_errata_probe(unsigned int stage,
> > >                               unsigned long archid, unsigned long impid)
> > >  {
> > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> > >         if (errata_probe_cmo(stage, archid, impid))
> > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> > >
> > > -       if (errata_probe_pmu(stage, archid, impid))
> > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > > -
> > >         return cpu_req_errata;
> > >  }
> > >
> > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > > index 4ed21a62158c..9bccc2ba0eb5 100644
> > > --- a/arch/riscv/include/asm/errata_list.h
> > > +++ b/arch/riscv/include/asm/errata_list.h
> > > @@ -25,8 +25,7 @@
> > >  #ifdef CONFIG_ERRATA_THEAD
> > >  #define        ERRATA_THEAD_PBMT 0
> > >  #define        ERRATA_THEAD_CMO 1
> > > -#define        ERRATA_THEAD_PMU 2
> > > -#define        ERRATA_THEAD_NUMBER 3
> > > +#define        ERRATA_THEAD_NUMBER 2
> > >  #endif
> > >
> > >  #ifdef __ASSEMBLY__
> > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> > >             "r"((unsigned long)(_start) + (_size))                      \
> > >         : "a0")
> > >
> > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > > -
> > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > -asm volatile(ALTERNATIVE(                                              \
> > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > > -       : "=r" (__ovl) :                                                \
> > > -       : "memory")
> > > -
> > >  #endif /* __ASSEMBLY__ */
> > >
> > >  #endif
> > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > index 5340f818746b..480f9da7fba7 100644
> > > --- a/arch/riscv/include/asm/hwcap.h
> > > +++ b/arch/riscv/include/asm/hwcap.h
> > > @@ -80,6 +80,7 @@
> > >  #define RISCV_ISA_EXT_ZFA              71
> > >  #define RISCV_ISA_EXT_ZTSO             72
> > >  #define RISCV_ISA_EXT_ZACAS            73
> > > +#define RISCV_ISA_EXT_XTHEADPMU                74
> > >
> > >  #define RISCV_ISA_EXT_MAX              128
> > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index e32591e9da90..4aded5bf8fc3 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> > >  };
> > >
> > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > > index 273d67ecf6d2..6cef15ec7c25 100644
> > > --- a/drivers/perf/Kconfig
> > > +++ b/drivers/perf/Kconfig
> > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> > >           full perf feature support i.e. counter overflow, privilege mode
> > >           filtering, counter configuration.
> > >
> > > +config THEAD_CUSTOM_PMU
> > > +       bool "T-Head custom PMU support"
> > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > > +       default y
> > > +       help
> > > +         The T-Head C9xx cores implement a PMU overflow extension very
> > > +         similar to the core SSCOFPMF extension.
> > > +
> > > +         This will patch the overflow CSR and handle the non-standard
> > > +         behaviour via the regular SBI PMU driver and interface.
> > > +
> > > +         If you don't know what to do here, say "Y".
> > > +
> > >  config ARM_PMU_ACPI
> > >         depends on ARM_PMU && ACPI
> > >         def_bool y
> > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > index 2edbc37abadf..31ca79846399 100644
> > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > @@ -20,10 +20,21 @@
> > >  #include <linux/cpu_pm.h>
> > >  #include <linux/sched/clock.h>
> > >
> > > -#include <asm/errata_list.h>
> > >  #include <asm/sbi.h>
> > >  #include <asm/cpufeature.h>
> > >
> > > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > > +
> > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > +asm volatile(ALTERNATIVE(                                              \
> > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > > +       : "=r" (__ovl) :                                                \
> > > +       : "memory")
> > > +
> > >  #define SYSCTL_NO_USER_ACCESS  0
> > >  #define SYSCTL_USER_ACCESS     1
> > >  #define SYSCTL_LEGACY          2
> > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> > >                 riscv_pmu_use_irq = true;
> > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > > -                  riscv_cached_marchid(0) == 0 &&
> > > -                  riscv_cached_mimpid(0) == 0) {
> > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> > >                 riscv_pmu_use_irq = true;
> > >         }
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > Regards,
> > Atish
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv



-- 
Regards,
Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 15807 bytes --]

On Wed, Jan 17, 2024 at 12:58:21AM -0800, Atish Patra wrote:
> On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> > > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > > <peterlin@andestech.com> wrote:
> > > >
> > > > The custom PMU extension aims to support perf event sampling prior
> > > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > > register reserved for future standard, a set of custom registers is
> > > > added.  Hence, we may consider it as a CPU feature rather than an
> > > > erratum.
> > > >
> > >
> > > I don't think we should do that. Any custom implementation that
> > > violates the standard RISC-V spec should
> > > be an errata not a feature.
> > > As per my understanding, a vendor can call an extension custom ISA
> > > extension if the same feature is not available
> > > in the standard ISA extensions or the mechanism is completely
> > > different. It must also not violate any standard spec as well.
> > >
> > > In this case, a standard sscofpmf is already available. Moreover, both
> > > Andes and T-head extensions violate the standard
> > > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > > are clearly specified as reserved for standard local interrupts
> > > in the AIA specification.
> >
> > I disagree with you here. The Andes implementation predated (IIRC that
> > is what was said in replies to an earlier revision) the Sscofpmf
> > extension and certainly predates the AIA specification. I would be on
> > board with this line of thinking if someone comes along in 2030 with
> > "Zbb but with this one tweak" or where something flies entirely in the
> > face of the standard (like the IOCP cache stuff). The relevant section
> > in the AIA spec seems to say:
> > | Interrupt causes that are standardized by the Privileged Architecture
> > | have major identities in the range 0–15, while numbers 16 and higher are
> > | officially available for platform standards or for custom use.
> > | The Advanced Interrupt Architecture claims further authority over
> > | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
> > | range 24–31 and all major identities 48 and higher still free for custom
> > | use.
> > I don't see how that can be problematic given the Andes implemtation
> > dates from before AIA was a thing. It would be silly to say that because
> > an optional extension later came along and took over something previously
> > allowed for indiscriminate custom use, that support for that custom
> > extension is not permitted.
> >
> 
> AIA is not some optional extension. It defines the RISC-V interrupt
> architecture going forward and will be the default implementation
> in the future.

I don't get you here. It is clearly optional - most (all?) existing
systems do not have it and certainly none did when this was designed.
The wording above from the AIA spec implies that using 16 and above used
to be okay for platform specifics (and I think the relevant section of
the priv spec was "Machine Interrupt Registers" which says the same).
New extensions coming along should not be allowed to block kernel
support for platform specifics that predated their use of permitted
"resources".

> IMO, this will be a slippery slope if we start
> supporting custom implementations to override interrupt ID definitions
> via custom cpu features. T-head implementation works perfectly fine as
> an errata and I don't understand why
> there is a push to make it a cpu feature.

I don't mind leaving the existing implementation (T-Head) using this,
but I will NAK any additions.

> We should try to improve the
> ecosystem for future platforms rather than bending
> backwards to support older implementations.

This is hardly "bending backwards".

Thanks,
Conor.

> I understand the push to brand this as a custom extension if current
> errata/alternative can't support it. But I don't think that's the case
> here though. Please correct me if I am wrong.
> 
> > I may well be missing something here though, you clearly know these
> > specs better than I do, but from what I have read I disagree.
> >
> > > Please implementation Andes PMU support as an errata as well similar to T-head
> >
> > I certainly _do not_ want to see things like this detected via lookup
> > tables of marchid and co in the kernel unless it is absolutely required.
> > We have standard probing mechanisms for feature detection (because to me
> > this _is_ a feature) and they should be used. Additionally, we define what
> > entries in the DT properties mean, and if it is convenient to put
> > "psuedo" extensions into the DT, then we should do so. Getting away from
> > being tied to what RVI decrees was one of the goals of the new
> > properties after all, so that we could use a standard mechanism of DT
> > probing for things like this.
> >
> 
> Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
> I'm sure we'll have many of those, which will be leveraged via pseudo
> extensions in the DT.
> However, these shouldn't co-exist with standard ISA extensions in the
> namespace in riscv_isa_ext and/or hwprobe.
> The vendor-specific extensions should be defined under a
> vendor-specific namespace.
> This was another issue with this series as well. I didn't raise this
> topic earlier because I don't think overriding interrupt
> identities qualifies for a custom ISA extension
> 
> > Thanks,
> > Conor.
> >
> > > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > > > for proper functioning as of this commit.
> > > >
> > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > > Reviewed-by: Guo Ren <guoren@kernel.org>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > ---
> > > > Changes v1 -> v2:
> > > >   - New patch
> > > > Changes v2 -> v3:
> > > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > > > Changes v3 -> v4:
> > > >   - No change
> > > > Changes v4 -> v5:
> > > >   - Include Guo's Reviewed-by
> > > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > > > Changes v5 -> v6:
> > > >   - Include Conor's Reviewed-by
> > > > Changes v6 -> v7:
> > > >   - No change
> > > > ---
> > > >  arch/riscv/Kconfig.errata            | 13 -------------
> > > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> > > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> > > >  arch/riscv/include/asm/hwcap.h       |  1 +
> > > >  arch/riscv/kernel/cpufeature.c       |  1 +
> > > >  drivers/perf/Kconfig                 | 13 +++++++++++++
> > > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> > > >  7 files changed, 30 insertions(+), 51 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > > index e2c731cfed8c..0d19f47d1018 100644
> > > > --- a/arch/riscv/Kconfig.errata
> > > > +++ b/arch/riscv/Kconfig.errata
> > > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> > > >
> > > >           If you don't know what to do here, say "Y".
> > > >
> > > > -config ERRATA_THEAD_PMU
> > > > -       bool "Apply T-Head PMU errata"
> > > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > > > -       default y
> > > > -       help
> > > > -         The T-Head C9xx cores implement a PMU overflow extension very
> > > > -         similar to the core SSCOFPMF extension.
> > > > -
> > > > -         This will apply the overflow errata to handle the non-standard
> > > > -         behaviour via the regular SBI PMU driver and interface.
> > > > -
> > > > -         If you don't know what to do here, say "Y".
> > > > -
> > > >  endmenu # "CPU errata selection"
> > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > > index 0554ed4bf087..5de5f7209132 100644
> > > > --- a/arch/riscv/errata/thead/errata.c
> > > > +++ b/arch/riscv/errata/thead/errata.c
> > > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> > > >         return true;
> > > >  }
> > > >
> > > > -static bool errata_probe_pmu(unsigned int stage,
> > > > -                            unsigned long arch_id, unsigned long impid)
> > > > -{
> > > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > > > -               return false;
> > > > -
> > > > -       /* target-c9xx cores report arch_id and impid as 0 */
> > > > -       if (arch_id != 0 || impid != 0)
> > > > -               return false;
> > > > -
> > > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > > -               return false;
> > > > -
> > > > -       return true;
> > > > -}
> > > > -
> > > >  static u32 thead_errata_probe(unsigned int stage,
> > > >                               unsigned long archid, unsigned long impid)
> > > >  {
> > > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> > > >         if (errata_probe_cmo(stage, archid, impid))
> > > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> > > >
> > > > -       if (errata_probe_pmu(stage, archid, impid))
> > > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > > > -
> > > >         return cpu_req_errata;
> > > >  }
> > > >
> > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > > > index 4ed21a62158c..9bccc2ba0eb5 100644
> > > > --- a/arch/riscv/include/asm/errata_list.h
> > > > +++ b/arch/riscv/include/asm/errata_list.h
> > > > @@ -25,8 +25,7 @@
> > > >  #ifdef CONFIG_ERRATA_THEAD
> > > >  #define        ERRATA_THEAD_PBMT 0
> > > >  #define        ERRATA_THEAD_CMO 1
> > > > -#define        ERRATA_THEAD_PMU 2
> > > > -#define        ERRATA_THEAD_NUMBER 3
> > > > +#define        ERRATA_THEAD_NUMBER 2
> > > >  #endif
> > > >
> > > >  #ifdef __ASSEMBLY__
> > > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> > > >             "r"((unsigned long)(_start) + (_size))                      \
> > > >         : "a0")
> > > >
> > > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > > > -
> > > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > -asm volatile(ALTERNATIVE(                                              \
> > > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > > > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > > > -       : "=r" (__ovl) :                                                \
> > > > -       : "memory")
> > > > -
> > > >  #endif /* __ASSEMBLY__ */
> > > >
> > > >  #endif
> > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > > index 5340f818746b..480f9da7fba7 100644
> > > > --- a/arch/riscv/include/asm/hwcap.h
> > > > +++ b/arch/riscv/include/asm/hwcap.h
> > > > @@ -80,6 +80,7 @@
> > > >  #define RISCV_ISA_EXT_ZFA              71
> > > >  #define RISCV_ISA_EXT_ZTSO             72
> > > >  #define RISCV_ISA_EXT_ZACAS            73
> > > > +#define RISCV_ISA_EXT_XTHEADPMU                74
> > > >
> > > >  #define RISCV_ISA_EXT_MAX              128
> > > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index e32591e9da90..4aded5bf8fc3 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> > > >  };
> > > >
> > > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > > > index 273d67ecf6d2..6cef15ec7c25 100644
> > > > --- a/drivers/perf/Kconfig
> > > > +++ b/drivers/perf/Kconfig
> > > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> > > >           full perf feature support i.e. counter overflow, privilege mode
> > > >           filtering, counter configuration.
> > > >
> > > > +config THEAD_CUSTOM_PMU
> > > > +       bool "T-Head custom PMU support"
> > > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > > > +       default y
> > > > +       help
> > > > +         The T-Head C9xx cores implement a PMU overflow extension very
> > > > +         similar to the core SSCOFPMF extension.
> > > > +
> > > > +         This will patch the overflow CSR and handle the non-standard
> > > > +         behaviour via the regular SBI PMU driver and interface.
> > > > +
> > > > +         If you don't know what to do here, say "Y".
> > > > +
> > > >  config ARM_PMU_ACPI
> > > >         depends on ARM_PMU && ACPI
> > > >         def_bool y
> > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > > index 2edbc37abadf..31ca79846399 100644
> > > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > > @@ -20,10 +20,21 @@
> > > >  #include <linux/cpu_pm.h>
> > > >  #include <linux/sched/clock.h>
> > > >
> > > > -#include <asm/errata_list.h>
> > > >  #include <asm/sbi.h>
> > > >  #include <asm/cpufeature.h>
> > > >
> > > > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > > > +
> > > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > +asm volatile(ALTERNATIVE(                                              \
> > > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > > > +       : "=r" (__ovl) :                                                \
> > > > +       : "memory")
> > > > +
> > > >  #define SYSCTL_NO_USER_ACCESS  0
> > > >  #define SYSCTL_USER_ACCESS     1
> > > >  #define SYSCTL_LEGACY          2
> > > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> > > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> > > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> > > >                 riscv_pmu_use_irq = true;
> > > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > > > -                  riscv_cached_marchid(0) == 0 &&
> > > > -                  riscv_cached_mimpid(0) == 0) {
> > > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> > > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> > > >                 riscv_pmu_use_irq = true;
> > > >         }
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > Regards,
> > > Atish
> 
> 
> 
> -- 
> Regards,
> Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Atish Patra]

On Wed, Jan 17, 2024 at 1:17 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Wed, Jan 17, 2024 at 12:58:21AM -0800, Atish Patra wrote:
> > On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> > > > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > > > <peterlin@andestech.com> wrote:
> > > > >
> > > > > The custom PMU extension aims to support perf event sampling prior
> > > > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > > > register reserved for future standard, a set of custom registers is
> > > > > added.  Hence, we may consider it as a CPU feature rather than an
> > > > > erratum.
> > > > >
> > > >
> > > > I don't think we should do that. Any custom implementation that
> > > > violates the standard RISC-V spec should
> > > > be an errata not a feature.
> > > > As per my understanding, a vendor can call an extension custom ISA
> > > > extension if the same feature is not available
> > > > in the standard ISA extensions or the mechanism is completely
> > > > different. It must also not violate any standard spec as well.
> > > >
> > > > In this case, a standard sscofpmf is already available. Moreover, both
> > > > Andes and T-head extensions violate the standard
> > > > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > > > are clearly specified as reserved for standard local interrupts
> > > > in the AIA specification.
> > >
> > > I disagree with you here. The Andes implementation predated (IIRC that
> > > is what was said in replies to an earlier revision) the Sscofpmf
> > > extension and certainly predates the AIA specification. I would be on
> > > board with this line of thinking if someone comes along in 2030 with
> > > "Zbb but with this one tweak" or where something flies entirely in the
> > > face of the standard (like the IOCP cache stuff). The relevant section
> > > in the AIA spec seems to say:
> > > | Interrupt causes that are standardized by the Privileged Architecture
> > > | have major identities in the range 0–15, while numbers 16 and higher are
> > > | officially available for platform standards or for custom use.
> > > | The Advanced Interrupt Architecture claims further authority over
> > > | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
> > > | range 24–31 and all major identities 48 and higher still free for custom
> > > | use.
> > > I don't see how that can be problematic given the Andes implemtation
> > > dates from before AIA was a thing. It would be silly to say that because
> > > an optional extension later came along and took over something previously
> > > allowed for indiscriminate custom use, that support for that custom
> > > extension is not permitted.
> > >
> >
> > AIA is not some optional extension. It defines the RISC-V interrupt
> > architecture going forward and will be the default implementation
> > in the future.
>
> I don't get you here. It is clearly optional - most (all?) existing
> systems do not have it and certainly none did when this was designed.

That's the current situation. I was saying AIA is not "some" optional extension
which most implementations will ignore in the future. In the future, I
expect most platforms
will implement AIA.

> The wording above from the AIA spec implies that using 16 and above used
> to be okay for platform specifics (and I think the relevant section of
> the priv spec was "Machine Interrupt Registers" which says the same).

As your quote also described above, AIA spec says (which overrides the
priv spec)

"The Advanced Interrupt Architecture claims further authority over
identity numbers in the ranges 16–23 and 32–47,
leaving numbers in the range 24–31 and all major identities 48 and
higher still free for custom use."

That means any implementation can be treated as custom (as per AIA
spec) if they choose a local interrupt
only in between 24-31 or > 48. Now if we choose to ignore the AIA spec
and go with the old priv spec statement to
decide if a custom implementation violated the standard encoding
space, that's a different argument. That means we have
to allow any future vendor implementation that violates as well as
long as they claim that they designed their chip before
AIA was ratified.

> New extensions coming along should not be allowed to block kernel
> support for platform specifics that predated their use of permitted
> "resources".
>
> > IMO, this will be a slippery slope if we start
> > supporting custom implementations to override interrupt ID definitions
> > via custom cpu features. T-head implementation works perfectly fine as
> > an errata and I don't understand why
> > there is a push to make it a cpu feature.
>
> I don't mind leaving the existing implementation (T-Head) using this,
> but I will NAK any additions.
>

That would be an ideal case where we won't require any additions
because all RISC-V vendor implementations
comply with the spec. In reality, we may not have that luxury ;)

> > We should try to improve the
> > ecosystem for future platforms rather than bending
> > backwards to support older implementations.
>
> This is hardly "bending backwards".
>
> Thanks,
> Conor.
>
> > I understand the push to brand this as a custom extension if current
> > errata/alternative can't support it. But I don't think that's the case
> > here though. Please correct me if I am wrong.
> >
> > > I may well be missing something here though, you clearly know these
> > > specs better than I do, but from what I have read I disagree.
> > >
> > > > Please implementation Andes PMU support as an errata as well similar to T-head
> > >
> > > I certainly _do not_ want to see things like this detected via lookup
> > > tables of marchid and co in the kernel unless it is absolutely required.
> > > We have standard probing mechanisms for feature detection (because to me
> > > this _is_ a feature) and they should be used. Additionally, we define what
> > > entries in the DT properties mean, and if it is convenient to put
> > > "psuedo" extensions into the DT, then we should do so. Getting away from
> > > being tied to what RVI decrees was one of the goals of the new
> > > properties after all, so that we could use a standard mechanism of DT
> > > probing for things like this.
> > >
> >
> > Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
> > I'm sure we'll have many of those, which will be leveraged via pseudo
> > extensions in the DT.
> > However, these shouldn't co-exist with standard ISA extensions in the
> > namespace in riscv_isa_ext and/or hwprobe.
> > The vendor-specific extensions should be defined under a
> > vendor-specific namespace.
> > This was another issue with this series as well. I didn't raise this
> > topic earlier because I don't think overriding interrupt
> > identities qualifies for a custom ISA extension
> >

Any thoughts on vendor specific namespace to avoid mixing standard ISA
extensions with vendor specific ones ?

> > > Thanks,
> > > Conor.
> > >
> > > > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > > > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > > > > for proper functioning as of this commit.
> > > > >
> > > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > > > Reviewed-by: Guo Ren <guoren@kernel.org>
> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > ---
> > > > > Changes v1 -> v2:
> > > > >   - New patch
> > > > > Changes v2 -> v3:
> > > > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > > > > Changes v3 -> v4:
> > > > >   - No change
> > > > > Changes v4 -> v5:
> > > > >   - Include Guo's Reviewed-by
> > > > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > > > > Changes v5 -> v6:
> > > > >   - Include Conor's Reviewed-by
> > > > > Changes v6 -> v7:
> > > > >   - No change
> > > > > ---
> > > > >  arch/riscv/Kconfig.errata            | 13 -------------
> > > > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> > > > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> > > > >  arch/riscv/include/asm/hwcap.h       |  1 +
> > > > >  arch/riscv/kernel/cpufeature.c       |  1 +
> > > > >  drivers/perf/Kconfig                 | 13 +++++++++++++
> > > > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> > > > >  7 files changed, 30 insertions(+), 51 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > > > index e2c731cfed8c..0d19f47d1018 100644
> > > > > --- a/arch/riscv/Kconfig.errata
> > > > > +++ b/arch/riscv/Kconfig.errata
> > > > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> > > > >
> > > > >           If you don't know what to do here, say "Y".
> > > > >
> > > > > -config ERRATA_THEAD_PMU
> > > > > -       bool "Apply T-Head PMU errata"
> > > > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > > > > -       default y
> > > > > -       help
> > > > > -         The T-Head C9xx cores implement a PMU overflow extension very
> > > > > -         similar to the core SSCOFPMF extension.
> > > > > -
> > > > > -         This will apply the overflow errata to handle the non-standard
> > > > > -         behaviour via the regular SBI PMU driver and interface.
> > > > > -
> > > > > -         If you don't know what to do here, say "Y".
> > > > > -
> > > > >  endmenu # "CPU errata selection"
> > > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > > > index 0554ed4bf087..5de5f7209132 100644
> > > > > --- a/arch/riscv/errata/thead/errata.c
> > > > > +++ b/arch/riscv/errata/thead/errata.c
> > > > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> > > > >         return true;
> > > > >  }
> > > > >
> > > > > -static bool errata_probe_pmu(unsigned int stage,
> > > > > -                            unsigned long arch_id, unsigned long impid)
> > > > > -{
> > > > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > > > > -               return false;
> > > > > -
> > > > > -       /* target-c9xx cores report arch_id and impid as 0 */
> > > > > -       if (arch_id != 0 || impid != 0)
> > > > > -               return false;
> > > > > -
> > > > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > > > -               return false;
> > > > > -
> > > > > -       return true;
> > > > > -}
> > > > > -
> > > > >  static u32 thead_errata_probe(unsigned int stage,
> > > > >                               unsigned long archid, unsigned long impid)
> > > > >  {
> > > > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> > > > >         if (errata_probe_cmo(stage, archid, impid))
> > > > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> > > > >
> > > > > -       if (errata_probe_pmu(stage, archid, impid))
> > > > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > > > > -
> > > > >         return cpu_req_errata;
> > > > >  }
> > > > >
> > > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > > > > index 4ed21a62158c..9bccc2ba0eb5 100644
> > > > > --- a/arch/riscv/include/asm/errata_list.h
> > > > > +++ b/arch/riscv/include/asm/errata_list.h
> > > > > @@ -25,8 +25,7 @@
> > > > >  #ifdef CONFIG_ERRATA_THEAD
> > > > >  #define        ERRATA_THEAD_PBMT 0
> > > > >  #define        ERRATA_THEAD_CMO 1
> > > > > -#define        ERRATA_THEAD_PMU 2
> > > > > -#define        ERRATA_THEAD_NUMBER 3
> > > > > +#define        ERRATA_THEAD_NUMBER 2
> > > > >  #endif
> > > > >
> > > > >  #ifdef __ASSEMBLY__
> > > > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> > > > >             "r"((unsigned long)(_start) + (_size))                      \
> > > > >         : "a0")
> > > > >
> > > > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > > > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > > > > -
> > > > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > > -asm volatile(ALTERNATIVE(                                              \
> > > > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > > > > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > > > > -       : "=r" (__ovl) :                                                \
> > > > > -       : "memory")
> > > > > -
> > > > >  #endif /* __ASSEMBLY__ */
> > > > >
> > > > >  #endif
> > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > > > index 5340f818746b..480f9da7fba7 100644
> > > > > --- a/arch/riscv/include/asm/hwcap.h
> > > > > +++ b/arch/riscv/include/asm/hwcap.h
> > > > > @@ -80,6 +80,7 @@
> > > > >  #define RISCV_ISA_EXT_ZFA              71
> > > > >  #define RISCV_ISA_EXT_ZTSO             72
> > > > >  #define RISCV_ISA_EXT_ZACAS            73
> > > > > +#define RISCV_ISA_EXT_XTHEADPMU                74
> > > > >
> > > > >  #define RISCV_ISA_EXT_MAX              128
> > > > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > > index e32591e9da90..4aded5bf8fc3 100644
> > > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > > > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > > > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > > > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > > > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> > > > >  };
> > > > >
> > > > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > > > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > > > > index 273d67ecf6d2..6cef15ec7c25 100644
> > > > > --- a/drivers/perf/Kconfig
> > > > > +++ b/drivers/perf/Kconfig
> > > > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> > > > >           full perf feature support i.e. counter overflow, privilege mode
> > > > >           filtering, counter configuration.
> > > > >
> > > > > +config THEAD_CUSTOM_PMU
> > > > > +       bool "T-Head custom PMU support"
> > > > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > > > > +       default y
> > > > > +       help
> > > > > +         The T-Head C9xx cores implement a PMU overflow extension very
> > > > > +         similar to the core SSCOFPMF extension.
> > > > > +
> > > > > +         This will patch the overflow CSR and handle the non-standard
> > > > > +         behaviour via the regular SBI PMU driver and interface.
> > > > > +
> > > > > +         If you don't know what to do here, say "Y".
> > > > > +
> > > > >  config ARM_PMU_ACPI
> > > > >         depends on ARM_PMU && ACPI
> > > > >         def_bool y
> > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > > > index 2edbc37abadf..31ca79846399 100644
> > > > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > > > @@ -20,10 +20,21 @@
> > > > >  #include <linux/cpu_pm.h>
> > > > >  #include <linux/sched/clock.h>
> > > > >
> > > > > -#include <asm/errata_list.h>
> > > > >  #include <asm/sbi.h>
> > > > >  #include <asm/cpufeature.h>
> > > > >
> > > > > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > > > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > > > > +
> > > > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > > +asm volatile(ALTERNATIVE(                                              \
> > > > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > > > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > > > > +       : "=r" (__ovl) :                                                \
> > > > > +       : "memory")
> > > > > +
> > > > >  #define SYSCTL_NO_USER_ACCESS  0
> > > > >  #define SYSCTL_USER_ACCESS     1
> > > > >  #define SYSCTL_LEGACY          2
> > > > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> > > > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> > > > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> > > > >                 riscv_pmu_use_irq = true;
> > > > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > > > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > > > > -                  riscv_cached_marchid(0) == 0 &&
> > > > > -                  riscv_cached_mimpid(0) == 0) {
> > > > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > > > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> > > > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> > > > >                 riscv_pmu_use_irq = true;
> > > > >         }
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > Regards,
> > > > Atish
> >
> >
> >
> > --
> > Regards,
> > Atish



-- 
Regards,
Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Conor Dooley]

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On Wed, Jan 17, 2024 at 02:32:59PM -0800, Atish Patra wrote:
> On Wed, Jan 17, 2024 at 1:17 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, Jan 17, 2024 at 12:58:21AM -0800, Atish Patra wrote:
> > > On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> > > > > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > > > > <peterlin@andestech.com> wrote:
> > > > > >
> > > > > > The custom PMU extension aims to support perf event sampling prior
> > > > > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > > > > register reserved for future standard, a set of custom registers is
> > > > > > added.  Hence, we may consider it as a CPU feature rather than an
> > > > > > erratum.
> > > > > >
> > > > >
> > > > > I don't think we should do that. Any custom implementation that
> > > > > violates the standard RISC-V spec should
> > > > > be an errata not a feature.
> > > > > As per my understanding, a vendor can call an extension custom ISA
> > > > > extension if the same feature is not available
> > > > > in the standard ISA extensions or the mechanism is completely
> > > > > different. It must also not violate any standard spec as well.
> > > > >
> > > > > In this case, a standard sscofpmf is already available. Moreover, both
> > > > > Andes and T-head extensions violate the standard
> > > > > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > > > > are clearly specified as reserved for standard local interrupts
> > > > > in the AIA specification.
> > > >
> > > > I disagree with you here. The Andes implementation predated (IIRC that
> > > > is what was said in replies to an earlier revision) the Sscofpmf
> > > > extension and certainly predates the AIA specification. I would be on
> > > > board with this line of thinking if someone comes along in 2030 with
> > > > "Zbb but with this one tweak" or where something flies entirely in the
> > > > face of the standard (like the IOCP cache stuff). The relevant section
> > > > in the AIA spec seems to say:
> > > > | Interrupt causes that are standardized by the Privileged Architecture
> > > > | have major identities in the range 0–15, while numbers 16 and higher are
> > > > | officially available for platform standards or for custom use.
> > > > | The Advanced Interrupt Architecture claims further authority over
> > > > | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
> > > > | range 24–31 and all major identities 48 and higher still free for custom
> > > > | use.
> > > > I don't see how that can be problematic given the Andes implemtation
> > > > dates from before AIA was a thing. It would be silly to say that because
> > > > an optional extension later came along and took over something previously
> > > > allowed for indiscriminate custom use, that support for that custom
> > > > extension is not permitted.
> > > >
> > >
> > > AIA is not some optional extension. It defines the RISC-V interrupt
> > > architecture going forward and will be the default implementation
> > > in the future.
> >
> > I don't get you here. It is clearly optional - most (all?) existing
> > systems do not have it and certainly none did when this was designed.
> 
> That's the current situation. I was saying AIA is not "some" optional extension
> which most implementations will ignore in the future. In the future, I
> expect most platforms will implement AIA.

In the future all platforms may, but I don't think that that is
particularly important here. The systems that we are talking about at
the moment do not have AIA. If there are AIA capable systems produced
using Andes' IP, one would hope that they implement Sscopmf (or w/e the
forgettable extension name is). :fingers_crossed:

> > The wording above from the AIA spec implies that using 16 and above used
> > to be okay for platform specifics (and I think the relevant section of
> > the priv spec was "Machine Interrupt Registers" which says the same).
> 
> As your quote also described above, AIA spec says (which overrides the
> priv spec)
> 
> "The Advanced Interrupt Architecture claims further authority over
> identity numbers in the ranges 16–23 and 32–47,
> leaving numbers in the range 24–31 and all major identities 48 and
> higher still free for custom use."
> 
> That means any implementation can be treated as custom (as per AIA
> spec) if they choose a local interrupt
> only in between 24-31 or > 48. Now if we choose to ignore the AIA spec
> and go with the old priv spec statement to
> decide if a custom implementation violated the standard encoding
> space, that's a different argument. That means we have
> to allow any future vendor implementation that violates as well as
> long as they claim that they designed their chip before
> AIA was ratified.

I don't see what the problem with that is. It is completely unreasonable
to render custom extensions that used the resources available to them at
the time invalid for use in the kernel (unless branded as an erratum)
because later on standard extensions co-opted those resources for its
own usage.

> > New extensions coming along should not be allowed to block kernel
> > support for platform specifics that predated their use of permitted
> > "resources".
> >
> > > IMO, this will be a slippery slope if we start
> > > supporting custom implementations to override interrupt ID definitions
> > > via custom cpu features. T-head implementation works perfectly fine as
> > > an errata and I don't understand why
> > > there is a push to make it a cpu feature.
> >
> > I don't mind leaving the existing implementation (T-Head) using this,
> > but I will NAK any additions.
> >
> 
> That would be an ideal case where we won't require any additions
> because all RISC-V vendor implementations
> comply with the spec. In reality, we may not have that luxury ;)

Where we have no other choice but to use marchid et al for detecting
issues with a vendors implementation, then I have no problem with it.
If you look at any of the threads where I have objected to the use of
them, it's been specifically for the detection of features, not for
their use in dealing with implementation issues (like the sifive sfence
issues).

> > > We should try to improve the
> > > ecosystem for future platforms rather than bending
> > > backwards to support older implementations.
> >
> > This is hardly "bending backwards".
> >
> > > I understand the push to brand this as a custom extension if current
> > > errata/alternative can't support it. But I don't think that's the case
> > > here though. Please correct me if I am wrong.
> > >
> > > > I may well be missing something here though, you clearly know these
> > > > specs better than I do, but from what I have read I disagree.
> > > >
> > > > > Please implementation Andes PMU support as an errata as well similar to T-head
> > > >
> > > > I certainly _do not_ want to see things like this detected via lookup
> > > > tables of marchid and co in the kernel unless it is absolutely required.
> > > > We have standard probing mechanisms for feature detection (because to me
> > > > this _is_ a feature) and they should be used. Additionally, we define what
> > > > entries in the DT properties mean, and if it is convenient to put
> > > > "psuedo" extensions into the DT, then we should do so. Getting away from
> > > > being tied to what RVI decrees was one of the goals of the new
> > > > properties after all, so that we could use a standard mechanism of DT
> > > > probing for things like this.
> > > >
> > >
> > > Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
> > > I'm sure we'll have many of those, which will be leveraged via pseudo
> > > extensions in the DT.
> > > However, these shouldn't co-exist with standard ISA extensions in the
> > > namespace in riscv_isa_ext and/or hwprobe.
> > > The vendor-specific extensions should be defined under a
> > > vendor-specific namespace.
> > > This was another issue with this series as well. I didn't raise this
> > > topic earlier because I don't think overriding interrupt
> > > identities qualifies for a custom ISA extension
> > >
> 
> Any thoughts on vendor specific namespace to avoid mixing standard ISA
> extensions with vendor specific ones ?

I don't really care for how it is exposed in hwprobe, you should ask
those responsible for the hwprobe interface what they think.

If you mean on the DT side, one of the stated goals of the new
properties was to put RVI's extensions and vendor extensions on a equal
footing.

Dunno if that answers your question,
Conor.

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Palmer Dabbelt]

On Wed, 17 Jan 2024 01:17:23 PST (-0800), Conor Dooley wrote:
> On Wed, Jan 17, 2024 at 12:58:21AM -0800, Atish Patra wrote:
>> On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
>> >
>> > On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
>> > > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
>> > > <peterlin@andestech.com> wrote:
>> > > >
>> > > > The custom PMU extension aims to support perf event sampling prior
>> > > > to the ratification of Sscofpmf. Instead of diverting the bits and
>> > > > register reserved for future standard, a set of custom registers is
>> > > > added.  Hence, we may consider it as a CPU feature rather than an
>> > > > erratum.
>> > > >
>> > >
>> > > I don't think we should do that. Any custom implementation that
>> > > violates the standard RISC-V spec should
>> > > be an errata not a feature.
>> > > As per my understanding, a vendor can call an extension custom ISA
>> > > extension if the same feature is not available
>> > > in the standard ISA extensions or the mechanism is completely
>> > > different. It must also not violate any standard spec as well.
>> > >
>> > > In this case, a standard sscofpmf is already available. Moreover, both
>> > > Andes and T-head extensions violate the standard
>> > > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
>> > > are clearly specified as reserved for standard local interrupts
>> > > in the AIA specification.
>> >
>> > I disagree with you here. The Andes implementation predated (IIRC that
>> > is what was said in replies to an earlier revision) the Sscofpmf
>> > extension and certainly predates the AIA specification. I would be on
>> > board with this line of thinking if someone comes along in 2030 with
>> > "Zbb but with this one tweak" or where something flies entirely in the
>> > face of the standard (like the IOCP cache stuff). The relevant section
>> > in the AIA spec seems to say:
>> > | Interrupt causes that are standardized by the Privileged Architecture
>> > | have major identities in the range 0–15, while numbers 16 and higher are
>> > | officially available for platform standards or for custom use.
>> > | The Advanced Interrupt Architecture claims further authority over
>> > | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
>> > | range 24–31 and all major identities 48 and higher still free for custom
>> > | use.
>> > I don't see how that can be problematic given the Andes implemtation
>> > dates from before AIA was a thing. It would be silly to say that because
>> > an optional extension later came along and took over something previously
>> > allowed for indiscriminate custom use, that support for that custom
>> > extension is not permitted.
>> >
>> 
>> AIA is not some optional extension. It defines the RISC-V interrupt
>> architecture going forward and will be the default implementation
>> in the future.
>
> I don't get you here. It is clearly optional - most (all?) existing
> systems do not have it and certainly none did when this was designed.
> The wording above from the AIA spec implies that using 16 and above used
> to be okay for platform specifics (and I think the relevant section of
> the priv spec was "Machine Interrupt Registers" which says the same).
> New extensions coming along should not be allowed to block kernel
> support for platform specifics that predated their use of permitted
> "resources".

Ya, the AIA stuff is definatley optional.  It's not even in the 
"everything's optional" grey area that's so common in RISC-V land, the 
AIA is a set of extensions and thus it's optional by design.

>> IMO, this will be a slippery slope if we start
>> supporting custom implementations to override interrupt ID definitions
>> via custom cpu features. T-head implementation works perfectly fine as
>> an errata and I don't understand why
>> there is a push to make it a cpu feature.
>
> I don't mind leaving the existing implementation (T-Head) using this,
> but I will NAK any additions.

I can't quite tell what the difference is here.  IMO whether we call 
something a feature or an errata doesn't really matter any more, it's 
just whatever framework happens to fit better.

>> We should try to improve the
>> ecosystem for future platforms rather than bending
>> backwards to support older implementations.
>
> This is hardly "bending backwards".

and even if it was, it'd be for real hardware and that's really what we 
should be focusing on.

> Thanks,
> Conor.
>
>> I understand the push to brand this as a custom extension if current
>> errata/alternative can't support it. But I don't think that's the case
>> here though. Please correct me if I am wrong.
>> 
>> > I may well be missing something here though, you clearly know these
>> > specs better than I do, but from what I have read I disagree.
>> >
>> > > Please implementation Andes PMU support as an errata as well similar to T-head
>> >
>> > I certainly _do not_ want to see things like this detected via lookup
>> > tables of marchid and co in the kernel unless it is absolutely required.
>> > We have standard probing mechanisms for feature detection (because to me
>> > this _is_ a feature) and they should be used. Additionally, we define what
>> > entries in the DT properties mean, and if it is convenient to put
>> > "psuedo" extensions into the DT, then we should do so. Getting away from
>> > being tied to what RVI decrees was one of the goals of the new
>> > properties after all, so that we could use a standard mechanism of DT
>> > probing for things like this.
>> >
>> 
>> Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
>> I'm sure we'll have many of those, which will be leveraged via pseudo
>> extensions in the DT.
>> However, these shouldn't co-exist with standard ISA extensions in the
>> namespace in riscv_isa_ext and/or hwprobe.
>> The vendor-specific extensions should be defined under a
>> vendor-specific namespace.
>> This was another issue with this series as well. I didn't raise this
>> topic earlier because I don't think overriding interrupt
>> identities qualifies for a custom ISA extension
>> 
>> > Thanks,
>> > Conor.
>> >
>> > > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
>> > > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
>> > > > for proper functioning as of this commit.
>> > > >
>> > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
>> > > > Reviewed-by: Guo Ren <guoren@kernel.org>
>> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> > > > ---
>> > > > Changes v1 -> v2:
>> > > >   - New patch
>> > > > Changes v2 -> v3:
>> > > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
>> > > > Changes v3 -> v4:
>> > > >   - No change
>> > > > Changes v4 -> v5:
>> > > >   - Include Guo's Reviewed-by
>> > > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
>> > > > Changes v5 -> v6:
>> > > >   - Include Conor's Reviewed-by
>> > > > Changes v6 -> v7:
>> > > >   - No change
>> > > > ---
>> > > >  arch/riscv/Kconfig.errata            | 13 -------------
>> > > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
>> > > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
>> > > >  arch/riscv/include/asm/hwcap.h       |  1 +
>> > > >  arch/riscv/kernel/cpufeature.c       |  1 +
>> > > >  drivers/perf/Kconfig                 | 13 +++++++++++++
>> > > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
>> > > >  7 files changed, 30 insertions(+), 51 deletions(-)
>> > > >
>> > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
>> > > > index e2c731cfed8c..0d19f47d1018 100644
>> > > > --- a/arch/riscv/Kconfig.errata
>> > > > +++ b/arch/riscv/Kconfig.errata
>> > > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
>> > > >
>> > > >           If you don't know what to do here, say "Y".
>> > > >
>> > > > -config ERRATA_THEAD_PMU
>> > > > -       bool "Apply T-Head PMU errata"
>> > > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
>> > > > -       default y
>> > > > -       help
>> > > > -         The T-Head C9xx cores implement a PMU overflow extension very
>> > > > -         similar to the core SSCOFPMF extension.
>> > > > -
>> > > > -         This will apply the overflow errata to handle the non-standard
>> > > > -         behaviour via the regular SBI PMU driver and interface.
>> > > > -
>> > > > -         If you don't know what to do here, say "Y".
>> > > > -
>> > > >  endmenu # "CPU errata selection"
>> > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
>> > > > index 0554ed4bf087..5de5f7209132 100644
>> > > > --- a/arch/riscv/errata/thead/errata.c
>> > > > +++ b/arch/riscv/errata/thead/errata.c
>> > > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
>> > > >         return true;
>> > > >  }
>> > > >
>> > > > -static bool errata_probe_pmu(unsigned int stage,
>> > > > -                            unsigned long arch_id, unsigned long impid)
>> > > > -{
>> > > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
>> > > > -               return false;
>> > > > -
>> > > > -       /* target-c9xx cores report arch_id and impid as 0 */
>> > > > -       if (arch_id != 0 || impid != 0)
>> > > > -               return false;
>> > > > -
>> > > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
>> > > > -               return false;
>> > > > -
>> > > > -       return true;
>> > > > -}
>> > > > -
>> > > >  static u32 thead_errata_probe(unsigned int stage,
>> > > >                               unsigned long archid, unsigned long impid)
>> > > >  {
>> > > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
>> > > >         if (errata_probe_cmo(stage, archid, impid))
>> > > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
>> > > >
>> > > > -       if (errata_probe_pmu(stage, archid, impid))
>> > > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
>> > > > -
>> > > >         return cpu_req_errata;
>> > > >  }
>> > > >
>> > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
>> > > > index 4ed21a62158c..9bccc2ba0eb5 100644
>> > > > --- a/arch/riscv/include/asm/errata_list.h
>> > > > +++ b/arch/riscv/include/asm/errata_list.h
>> > > > @@ -25,8 +25,7 @@
>> > > >  #ifdef CONFIG_ERRATA_THEAD
>> > > >  #define        ERRATA_THEAD_PBMT 0
>> > > >  #define        ERRATA_THEAD_CMO 1
>> > > > -#define        ERRATA_THEAD_PMU 2
>> > > > -#define        ERRATA_THEAD_NUMBER 3
>> > > > +#define        ERRATA_THEAD_NUMBER 2
>> > > >  #endif
>> > > >
>> > > >  #ifdef __ASSEMBLY__
>> > > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
>> > > >             "r"((unsigned long)(_start) + (_size))                      \
>> > > >         : "a0")
>> > > >
>> > > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
>> > > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
>> > > > -
>> > > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
>> > > > -asm volatile(ALTERNATIVE(                                              \
>> > > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
>> > > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
>> > > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
>> > > > -               CONFIG_ERRATA_THEAD_PMU)                                \
>> > > > -       : "=r" (__ovl) :                                                \
>> > > > -       : "memory")
>> > > > -
>> > > >  #endif /* __ASSEMBLY__ */
>> > > >
>> > > >  #endif
>> > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> > > > index 5340f818746b..480f9da7fba7 100644
>> > > > --- a/arch/riscv/include/asm/hwcap.h
>> > > > +++ b/arch/riscv/include/asm/hwcap.h
>> > > > @@ -80,6 +80,7 @@
>> > > >  #define RISCV_ISA_EXT_ZFA              71
>> > > >  #define RISCV_ISA_EXT_ZTSO             72
>> > > >  #define RISCV_ISA_EXT_ZACAS            73
>> > > > +#define RISCV_ISA_EXT_XTHEADPMU                74
>> > > >
>> > > >  #define RISCV_ISA_EXT_MAX              128
>> > > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
>> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> > > > index e32591e9da90..4aded5bf8fc3 100644
>> > > > --- a/arch/riscv/kernel/cpufeature.c
>> > > > +++ b/arch/riscv/kernel/cpufeature.c
>> > > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>> > > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
>> > > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
>> > > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
>> > > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
>> > > >  };
>> > > >
>> > > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
>> > > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
>> > > > index 273d67ecf6d2..6cef15ec7c25 100644
>> > > > --- a/drivers/perf/Kconfig
>> > > > +++ b/drivers/perf/Kconfig
>> > > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
>> > > >           full perf feature support i.e. counter overflow, privilege mode
>> > > >           filtering, counter configuration.
>> > > >
>> > > > +config THEAD_CUSTOM_PMU
>> > > > +       bool "T-Head custom PMU support"
>> > > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
>> > > > +       default y
>> > > > +       help
>> > > > +         The T-Head C9xx cores implement a PMU overflow extension very
>> > > > +         similar to the core SSCOFPMF extension.
>> > > > +
>> > > > +         This will patch the overflow CSR and handle the non-standard
>> > > > +         behaviour via the regular SBI PMU driver and interface.
>> > > > +
>> > > > +         If you don't know what to do here, say "Y".
>> > > > +
>> > > >  config ARM_PMU_ACPI
>> > > >         depends on ARM_PMU && ACPI
>> > > >         def_bool y
>> > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
>> > > > index 2edbc37abadf..31ca79846399 100644
>> > > > --- a/drivers/perf/riscv_pmu_sbi.c
>> > > > +++ b/drivers/perf/riscv_pmu_sbi.c
>> > > > @@ -20,10 +20,21 @@
>> > > >  #include <linux/cpu_pm.h>
>> > > >  #include <linux/sched/clock.h>
>> > > >
>> > > > -#include <asm/errata_list.h>
>> > > >  #include <asm/sbi.h>
>> > > >  #include <asm/cpufeature.h>
>> > > >
>> > > > +#define THEAD_C9XX_RV_IRQ_PMU          17
>> > > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
>> > > > +
>> > > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
>> > > > +asm volatile(ALTERNATIVE(                                              \
>> > > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
>> > > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
>> > > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
>> > > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
>> > > > +       : "=r" (__ovl) :                                                \
>> > > > +       : "memory")
>> > > > +
>> > > >  #define SYSCTL_NO_USER_ACCESS  0
>> > > >  #define SYSCTL_USER_ACCESS     1
>> > > >  #define SYSCTL_LEGACY          2
>> > > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
>> > > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
>> > > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
>> > > >                 riscv_pmu_use_irq = true;
>> > > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
>> > > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
>> > > > -                  riscv_cached_marchid(0) == 0 &&
>> > > > -                  riscv_cached_mimpid(0) == 0) {
>> > > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
>> > > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
>> > > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
>> > > >                 riscv_pmu_use_irq = true;
>> > > >         }
>> > > > --
>> > > > 2.34.1
>> > > >
>> > >
>> > >
>> > > --
>> > > Regards,
>> > > Atish
>> 
>> 
>> 
>> -- 
>> Regards,
>> Atish

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Re: [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework

[Yu-Chien Peter Lin]

Thank you all for your opinion,
In fact, the Sscofpmf has been implemented in Andes cores newer than
AX45, which is the last one to support Andes PMU. Additionally, this
feature will be switched to Sscofpmf once Andes core supports AIA.

On Wed, Jan 17, 2024 at 12:58:21AM -0800, Atish Patra wrote:
> On Tue, Jan 16, 2024 at 4:16 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Tue, Jan 16, 2024 at 12:55:41PM -0800, Atish Patra wrote:
> > > On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> > > <peterlin@andestech.com> wrote:
> > > >
> > > > The custom PMU extension aims to support perf event sampling prior
> > > > to the ratification of Sscofpmf. Instead of diverting the bits and
> > > > register reserved for future standard, a set of custom registers is
> > > > added.  Hence, we may consider it as a CPU feature rather than an
> > > > erratum.
> > > >
> > >
> > > I don't think we should do that. Any custom implementation that
> > > violates the standard RISC-V spec should
> > > be an errata not a feature.
> > > As per my understanding, a vendor can call an extension custom ISA
> > > extension if the same feature is not available
> > > in the standard ISA extensions or the mechanism is completely
> > > different. It must also not violate any standard spec as well.
> > >
> > > In this case, a standard sscofpmf is already available. Moreover, both
> > > Andes and T-head extensions violate the standard
> > > spec by reusing local interrupt numbers (17(Thead) & 18(Andes)) which
> > > are clearly specified as reserved for standard local interrupts
> > > in the AIA specification.
> >
> > I disagree with you here. The Andes implementation predated (IIRC that
> > is what was said in replies to an earlier revision) the Sscofpmf
> > extension and certainly predates the AIA specification. I would be on
> > board with this line of thinking if someone comes along in 2030 with
> > "Zbb but with this one tweak" or where something flies entirely in the
> > face of the standard (like the IOCP cache stuff). The relevant section
> > in the AIA spec seems to say:
> > | Interrupt causes that are standardized by the Privileged Architecture
> > | have major identities in the range 0–15, while numbers 16 and higher are
> > | officially available for platform standards or for custom use.
> > | The Advanced Interrupt Architecture claims further authority over
> > | identity numbers in the ranges 16–23 and 32–47, leaving numbers in the
> > | range 24–31 and all major identities 48 and higher still free for custom
> > | use.
> > I don't see how that can be problematic given the Andes implemtation
> > dates from before AIA was a thing. It would be silly to say that because
> > an optional extension later came along and took over something previously
> > allowed for indiscriminate custom use, that support for that custom
> > extension is not permitted.
> >
> 
> AIA is not some optional extension. It defines the RISC-V interrupt
> architecture going forward and will be the default implementation
> in the future. IMO, this will be a slippery slope if we start
> supporting custom implementations to override interrupt ID definitions
> via custom cpu features. T-head implementation works perfectly fine as
> an errata and I don't understand why
> there is a push to make it a cpu feature. We should try to improve the
> ecosystem for future platforms rather than bending
> backwards to support older implementations.
> 
> I understand the push to brand this as a custom extension if current
> errata/alternative can't support it. But I don't think that's the case
> here though. Please correct me if I am wrong.
> 
> > I may well be missing something here though, you clearly know these
> > specs better than I do, but from what I have read I disagree.
> >
> > > Please implementation Andes PMU support as an errata as well similar to T-head
> >
> > I certainly _do not_ want to see things like this detected via lookup
> > tables of marchid and co in the kernel unless it is absolutely required.
> > We have standard probing mechanisms for feature detection (because to me
> > this _is_ a feature) and they should be used. Additionally, we define what
> > entries in the DT properties mean, and if it is convenient to put
> > "psuedo" extensions into the DT, then we should do so. Getting away from
> > being tied to what RVI decrees was one of the goals of the new
> > properties after all, so that we could use a standard mechanism of DT
> > probing for things like this.
> >
> 
> Yes. That's a perfectly valid mechanism for actual custom/vendor ISA extensions.
> I'm sure we'll have many of those, which will be leveraged via pseudo
> extensions in the DT.
> However, these shouldn't co-exist with standard ISA extensions in the
> namespace in riscv_isa_ext and/or hwprobe.
> The vendor-specific extensions should be defined under a
> vendor-specific namespace.

I will remove T-Head PMU changes from this series.
Could you please elaborate a bit more on how should I add a vendor-specific
extension?

Thanks,
Peter Lin

> This was another issue with this series as well. I didn't raise this
> topic earlier because I don't think overriding interrupt
> identities qualifies for a custom ISA extension
> 
> > Thanks,
> > Conor.
> >
> > > > T-Head cores need to append "xtheadpmu" to the riscv,isa-extensions
> > > > for each cpu node in device tree, and enable CONFIG_THEAD_CUSTOM_PMU
> > > > for proper functioning as of this commit.
> > > >
> > > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > > > Reviewed-by: Guo Ren <guoren@kernel.org>
> > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > ---
> > > > Changes v1 -> v2:
> > > >   - New patch
> > > > Changes v2 -> v3:
> > > >   - Removed m{vendor/arch/imp}id checks in pmu_sbi_setup_irqs()
> > > > Changes v3 -> v4:
> > > >   - No change
> > > > Changes v4 -> v5:
> > > >   - Include Guo's Reviewed-by
> > > >   - Let THEAD_CUSTOM_PMU depend on ARCH_THEAD
> > > > Changes v5 -> v6:
> > > >   - Include Conor's Reviewed-by
> > > > Changes v6 -> v7:
> > > >   - No change
> > > > ---
> > > >  arch/riscv/Kconfig.errata            | 13 -------------
> > > >  arch/riscv/errata/thead/errata.c     | 19 -------------------
> > > >  arch/riscv/include/asm/errata_list.h | 15 +--------------
> > > >  arch/riscv/include/asm/hwcap.h       |  1 +
> > > >  arch/riscv/kernel/cpufeature.c       |  1 +
> > > >  drivers/perf/Kconfig                 | 13 +++++++++++++
> > > >  drivers/perf/riscv_pmu_sbi.c         | 19 ++++++++++++++-----
> > > >  7 files changed, 30 insertions(+), 51 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > > index e2c731cfed8c..0d19f47d1018 100644
> > > > --- a/arch/riscv/Kconfig.errata
> > > > +++ b/arch/riscv/Kconfig.errata
> > > > @@ -86,17 +86,4 @@ config ERRATA_THEAD_CMO
> > > >
> > > >           If you don't know what to do here, say "Y".
> > > >
> > > > -config ERRATA_THEAD_PMU
> > > > -       bool "Apply T-Head PMU errata"
> > > > -       depends on ERRATA_THEAD && RISCV_PMU_SBI
> > > > -       default y
> > > > -       help
> > > > -         The T-Head C9xx cores implement a PMU overflow extension very
> > > > -         similar to the core SSCOFPMF extension.
> > > > -
> > > > -         This will apply the overflow errata to handle the non-standard
> > > > -         behaviour via the regular SBI PMU driver and interface.
> > > > -
> > > > -         If you don't know what to do here, say "Y".
> > > > -
> > > >  endmenu # "CPU errata selection"
> > > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > > index 0554ed4bf087..5de5f7209132 100644
> > > > --- a/arch/riscv/errata/thead/errata.c
> > > > +++ b/arch/riscv/errata/thead/errata.c
> > > > @@ -53,22 +53,6 @@ static bool errata_probe_cmo(unsigned int stage,
> > > >         return true;
> > > >  }
> > > >
> > > > -static bool errata_probe_pmu(unsigned int stage,
> > > > -                            unsigned long arch_id, unsigned long impid)
> > > > -{
> > > > -       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
> > > > -               return false;
> > > > -
> > > > -       /* target-c9xx cores report arch_id and impid as 0 */
> > > > -       if (arch_id != 0 || impid != 0)
> > > > -               return false;
> > > > -
> > > > -       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > > > -               return false;
> > > > -
> > > > -       return true;
> > > > -}
> > > > -
> > > >  static u32 thead_errata_probe(unsigned int stage,
> > > >                               unsigned long archid, unsigned long impid)
> > > >  {
> > > > @@ -80,9 +64,6 @@ static u32 thead_errata_probe(unsigned int stage,
> > > >         if (errata_probe_cmo(stage, archid, impid))
> > > >                 cpu_req_errata |= BIT(ERRATA_THEAD_CMO);
> > > >
> > > > -       if (errata_probe_pmu(stage, archid, impid))
> > > > -               cpu_req_errata |= BIT(ERRATA_THEAD_PMU);
> > > > -
> > > >         return cpu_req_errata;
> > > >  }
> > > >
> > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > > > index 4ed21a62158c..9bccc2ba0eb5 100644
> > > > --- a/arch/riscv/include/asm/errata_list.h
> > > > +++ b/arch/riscv/include/asm/errata_list.h
> > > > @@ -25,8 +25,7 @@
> > > >  #ifdef CONFIG_ERRATA_THEAD
> > > >  #define        ERRATA_THEAD_PBMT 0
> > > >  #define        ERRATA_THEAD_CMO 1
> > > > -#define        ERRATA_THEAD_PMU 2
> > > > -#define        ERRATA_THEAD_NUMBER 3
> > > > +#define        ERRATA_THEAD_NUMBER 2
> > > >  #endif
> > > >
> > > >  #ifdef __ASSEMBLY__
> > > > @@ -147,18 +146,6 @@ asm volatile(ALTERNATIVE_2(                                                \
> > > >             "r"((unsigned long)(_start) + (_size))                      \
> > > >         : "a0")
> > > >
> > > > -#define THEAD_C9XX_RV_IRQ_PMU                  17
> > > > -#define THEAD_C9XX_CSR_SCOUNTEROF              0x5c5
> > > > -
> > > > -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > -asm volatile(ALTERNATIVE(                                              \
> > > > -       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > -       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > -               THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
> > > > -               CONFIG_ERRATA_THEAD_PMU)                                \
> > > > -       : "=r" (__ovl) :                                                \
> > > > -       : "memory")
> > > > -
> > > >  #endif /* __ASSEMBLY__ */
> > > >
> > > >  #endif
> > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > > index 5340f818746b..480f9da7fba7 100644
> > > > --- a/arch/riscv/include/asm/hwcap.h
> > > > +++ b/arch/riscv/include/asm/hwcap.h
> > > > @@ -80,6 +80,7 @@
> > > >  #define RISCV_ISA_EXT_ZFA              71
> > > >  #define RISCV_ISA_EXT_ZTSO             72
> > > >  #define RISCV_ISA_EXT_ZACAS            73
> > > > +#define RISCV_ISA_EXT_XTHEADPMU                74
> > > >
> > > >  #define RISCV_ISA_EXT_MAX              128
> > > >  #define RISCV_ISA_EXT_INVALID          U32_MAX
> > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > > index e32591e9da90..4aded5bf8fc3 100644
> > > > --- a/arch/riscv/kernel/cpufeature.c
> > > > +++ b/arch/riscv/kernel/cpufeature.c
> > > > @@ -303,6 +303,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > > >         __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
> > > >         __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
> > > >         __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> > > > +       __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU),
> > > >  };
> > > >
> > > >  const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
> > > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> > > > index 273d67ecf6d2..6cef15ec7c25 100644
> > > > --- a/drivers/perf/Kconfig
> > > > +++ b/drivers/perf/Kconfig
> > > > @@ -86,6 +86,19 @@ config RISCV_PMU_SBI
> > > >           full perf feature support i.e. counter overflow, privilege mode
> > > >           filtering, counter configuration.
> > > >
> > > > +config THEAD_CUSTOM_PMU
> > > > +       bool "T-Head custom PMU support"
> > > > +       depends on ARCH_THEAD && RISCV_ALTERNATIVE && RISCV_PMU_SBI
> > > > +       default y
> > > > +       help
> > > > +         The T-Head C9xx cores implement a PMU overflow extension very
> > > > +         similar to the core SSCOFPMF extension.
> > > > +
> > > > +         This will patch the overflow CSR and handle the non-standard
> > > > +         behaviour via the regular SBI PMU driver and interface.
> > > > +
> > > > +         If you don't know what to do here, say "Y".
> > > > +
> > > >  config ARM_PMU_ACPI
> > > >         depends on ARM_PMU && ACPI
> > > >         def_bool y
> > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> > > > index 2edbc37abadf..31ca79846399 100644
> > > > --- a/drivers/perf/riscv_pmu_sbi.c
> > > > +++ b/drivers/perf/riscv_pmu_sbi.c
> > > > @@ -20,10 +20,21 @@
> > > >  #include <linux/cpu_pm.h>
> > > >  #include <linux/sched/clock.h>
> > > >
> > > > -#include <asm/errata_list.h>
> > > >  #include <asm/sbi.h>
> > > >  #include <asm/cpufeature.h>
> > > >
> > > > +#define THEAD_C9XX_RV_IRQ_PMU          17
> > > > +#define THEAD_C9XX_CSR_SCOUNTEROF      0x5c5
> > > > +
> > > > +#define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
> > > > +asm volatile(ALTERNATIVE(                                              \
> > > > +       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
> > > > +       "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
> > > > +               0, RISCV_ISA_EXT_XTHEADPMU,                             \
> > > > +               CONFIG_THEAD_CUSTOM_PMU)                                \
> > > > +       : "=r" (__ovl) :                                                \
> > > > +       : "memory")
> > > > +
> > > >  #define SYSCTL_NO_USER_ACCESS  0
> > > >  #define SYSCTL_USER_ACCESS     1
> > > >  #define SYSCTL_LEGACY          2
> > > > @@ -808,10 +819,8 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
> > > >         if (riscv_isa_extension_available(NULL, SSCOFPMF)) {
> > > >                 riscv_pmu_irq_num = RV_IRQ_PMU;
> > > >                 riscv_pmu_use_irq = true;
> > > > -       } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> > > > -                  riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> > > > -                  riscv_cached_marchid(0) == 0 &&
> > > > -                  riscv_cached_mimpid(0) == 0) {
> > > > +       } else if (riscv_isa_extension_available(NULL, XTHEADPMU) &&
> > > > +                  IS_ENABLED(CONFIG_THEAD_CUSTOM_PMU)) {
> > > >                 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
> > > >                 riscv_pmu_use_irq = true;
> > > >         }
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > Regards,
> > > Atish
> 
> 
> 
> -- 
> Regards,
> Atish

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