From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Atish Patra <atishp@atishpatra.org>, Anup Patel <anup@brainfault.org>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Cyril.Jean@microchip.com,
Daire McNamara <daire.mcnamara@microchip.com>,
Anup Patel <anup.patel@wdc.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Alistair Francis <alistair.francis@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Padmarao Begari <padmarao.begari@microchip.com>
Subject: Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
Date: Tue, 3 Nov 2020 10:59:34 +0000 [thread overview]
Message-ID: <734904fe-975a-5908-d08c-266a5049deac@codethink.co.uk> (raw)
In-Reply-To: <CAOnJCUKCbkZVGX5Rjputs9QQAHCvH6Fikt7kVGsyCkNjbdMv=Q@mail.gmail.com>
On 30/10/2020 20:27, Atish Patra wrote:
> On Fri, Oct 30, 2020 at 2:05 AM Anup Patel <anup@brainfault.org> wrote:
>>
>> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra <atish.patra@wdc.com> wrote:
>>>
>>> Add initial DTS for Microchip ICICLE board having only
>>> essential devcies (clocks, sdhci, ethernet, serial, etc).
>>>
>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>> ---
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/microchip/Makefile | 2 +
>>> .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++
>>
>> I suggest we split this DTS into two parts:
>> 1. SOC (microchip-polarfire.dtsi)
>> 2. Board (microchip-icicle-kit-a000.dts)
>>
>> This will be much cleaner and aligned with what is done
>> on other architectures.
>>
>
> Sure. I will do that in v2.
>
>>> 3 files changed, 316 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>>
>>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
>>> index ca1f8cbd78c0..3ea94ea0a18a 100644
>>> --- a/arch/riscv/boot/dts/Makefile
>>> +++ b/arch/riscv/boot/dts/Makefile
>>> @@ -1,5 +1,6 @@
>>> # SPDX-License-Identifier: GPL-2.0
>>> subdir-y += sifive
>>> subdir-y += kendryte
>>> +subdir-y += microchip
>>>
>>> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
>>> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
>>> new file mode 100644
>>> index 000000000000..55ad77521304
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/Makefile
>>> @@ -0,0 +1,2 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-icicle-kit-a000.dtb
>>> diff --git a/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> new file mode 100644
>>> index 000000000000..5848920af55c
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts
>>> @@ -0,0 +1,313 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/* Copyright (c) 2020 Microchip Technology Inc */
>>> +
>>> +/dts-v1/;
>>> +
>>> +/* Clock frequency (in Hz) of the rtcclk */
>>> +#define RTCCLK_FREQ 1000000
>>> +
>>> +/ {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + model = "Microchip PolarFire-SoC";
>>> + compatible = "microchip,polarfire-soc";
>>> +
>>> + chosen {
>>> + stdout-path = &serial0;
>>> + };
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + timebase-frequency = <RTCCLK_FREQ>;
>>> +
>>> + cpu@0 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <128>;
>>> + i-cache-size = <16384>;
>>> + reg = <0>;
>>> + riscv,isa = "rv64imac";
>>> + status = "disabled";
>>> +
>>> + cpu0_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@1 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <1>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu1_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@2 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <2>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu2_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@3 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <3>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> +
>>> + cpu3_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> +
>>> + cpu@4 {
>>> + clock-frequency = <0>;
>>> + compatible = "sifive,rocket0", "riscv";
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <64>;
>>> + d-cache-size = <32768>;
>>> + d-tlb-sets = <1>;
>>> + d-tlb-size = <32>;
>>> + device_type = "cpu";
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <64>;
>>> + i-cache-size = <32768>;
>>> + i-tlb-sets = <1>;
>>> + i-tlb-size = <32>;
>>> + mmu-type = "riscv,sv39";
>>> + reg = <4>;
>>> + riscv,isa = "rv64imafdc";
>>> + tlb-split;
>>> + status = "okay";
>>> + cpu4_intc: interrupt-controller {
>>> + #interrupt-cells = <1>;
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + };
>>> + };
>>> + };
>>> +
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> + reg = <0x0 0x80000000 0x0 0x40000000>;
>>> + clocks = <&clkcfg 26>;
>>> + };
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + cache-controller@2010000 {
>>> + compatible = "sifive,fu540-c000-ccache", "cache";
>>> + cache-block-size = <64>;
>>> + cache-level = <2>;
>>> + cache-sets = <1024>;
>>> + cache-size = <2097152>;
>>> + cache-unified;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <1 2 3>;
>>> + reg = <0x0 0x2010000 0x0 0x1000>;
>>> + };
>>> +
>>> + clint@2000000 {
>>> + compatible = "riscv,clint0";
>>> + reg = <0x0 0x2000000 0x0 0xC000>;
>>> + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>>> + &cpu1_intc 3 &cpu1_intc 7
>>> + &cpu2_intc 3 &cpu2_intc 7
>>> + &cpu3_intc 3 &cpu3_intc 7
>>> + &cpu4_intc 3 &cpu4_intc 7>;
>>> + };
>>> +
>>> + plic: interrupt-controller@c000000 {
>>> + #interrupt-cells = <1>;
>>> + compatible = "sifive,plic-1.0.0";
>>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>>> + riscv,ndev = <53>;
>>> + interrupt-controller;
>>> + interrupts-extended = <&cpu0_intc 11
>>> + &cpu1_intc 11 &cpu1_intc 9
>>> + &cpu2_intc 11 &cpu2_intc 9
>>> + &cpu3_intc 11 &cpu3_intc 9
>>> + &cpu4_intc 11 &cpu4_intc 9>;
>>> + };
>>> +
>>> + dma@3000000 {
>>> + compatible = "sifive,fu540-c000-pdma";
>>> + reg = <0x0 0x3000000 0x0 0x8000>;
>>> + interrupt-parent = <&plic>;
>>> + interrupts = <23 24 25 26 27 28 29 30>;
>>> + #dma-cells = <1>;
>>> + };
>>> +
>>> + refclk: refclk {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <600000000>;
>>> + clock-output-names = "msspllclk";
>>> + };
>>> +
>>> + clkcfg: clkcfg@20002000 {
>>> + compatible = "microchip,pfsoc-clkcfg";
>>> + reg = <0x0 0x20002000 0x0 0x1000>;
>>> + reg-names = "mss_sysreg";
>>> + clocks = <&refclk>;
>>> + #clock-cells = <1>;
>>> + clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
>>> + };
>>> +
H ow about doing something like
> clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", /* 0 -4 */
> "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", /* 5-9 */
this means we can easily work out what clocks are in which index
As per the previos email, I'd leave these all populated as coming back
and adding ones later is just going to be a pain with merge conflicts.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-11-03 11:00 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30 9:08 ` Anup Patel
2020-11-03 9:55 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24 ` Ben Dooks
2020-10-30 7:11 ` Atish Patra
2020-10-30 21:19 ` Ben Dooks
2020-11-03 15:07 ` Atish Patra
2020-11-03 15:19 ` Ben Dooks
2020-11-03 18:10 ` Cyril.Jean
2020-11-03 18:28 ` Ben Dooks
2020-11-03 18:36 ` Atish Patra
2020-11-03 18:39 ` Ben Dooks
2020-11-03 18:45 ` Atish Patra
2020-11-03 18:40 ` Cyril.Jean
2020-11-03 18:46 ` Ben Dooks
2020-11-04 2:41 ` Bin Meng
2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
2020-11-03 10:59 ` Ben Dooks [this message]
2020-11-03 15:08 ` Atish Patra
2020-10-30 21:20 ` Ben Dooks
2020-11-03 10:00 ` Bin Meng
2020-11-03 18:19 ` Cyril.Jean
2020-11-03 18:38 ` Atish Patra
2020-11-03 18:50 ` Cyril.Jean
2020-11-03 19:02 ` Atish Patra
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30 9:09 ` Anup Patel
2020-10-30 21:21 ` Ben Dooks
2020-11-03 10:03 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-11-06 7:37 ` Atish Patra
2020-11-06 8:11 ` Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=734904fe-975a-5908-d08c-266a5049deac@codethink.co.uk \
--to=ben.dooks@codethink.co.uk \
--cc=Cyril.Jean@microchip.com \
--cc=alistair.francis@wdc.com \
--cc=anup.patel@wdc.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=atishp@atishpatra.org \
--cc=daire.mcnamara@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=padmarao.begari@microchip.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).